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IDTCV104B Datasheet

  • IDTCV104B

  • CLOCK GENERATOR FOR DESKTOP PC PLATFORMS

  • 21頁(yè)

  • IDT

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IDTCV104B
CLOCK GENERATOR FOR DESKTOP PC PLATFORMS
COMMERCIAL TEMPERATURE RANGE
CLOCK GENERATOR FOR
DESKTOP PC PLATFORMS
IDTCV104B
PRELIMINARY
FEATURES:
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4 PLL architecture
Linear frequency programming
Independent frequency programming and SSC control
Band-gap circuit for differential output
High power-noise rejection ratio
66MHz to 533MHz CPU frequency
VCO frequency up to 1.1G
Support index block read/write, single cycle index block read
Programmable REF, 3V66, PCI, 48MHz I/O drive strength
Programmable 3V66 and PCI Skew
Available in SSOP package
IDTCV104B is a 48 pin clock generation device for desktop PC platforms.
This chip incorporates four PLLs to allow independent generation of CPU, AGP/
PCI, SRC, and 48MHz clocks. The dedicated PLL for Serial ATA clock
provides high accuracy frequency. This device also implements Band-gap
referenced I
REF
to reduce the impact of V
DD
variation on differential outputs,
which can provide more robust system performance.
Static PLL frequency divide error can be as low as 36 ppm, providing high
accuracy output clock. Each CPU, AGP/PCI, SRC clock has its own Spread
Spectrum selection.
DESCRIPTION:
KEY SPECIFICATION:
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CPU/SRC CLK cycle to cycle jitter < 125ps
SATA CLK cycle to cycle jitter < 125ps
PCI CLK cycle to cycle jitter < 250ps
Static PLL frequency divide error as low as 36ppm
FUNCTIONAL BLOCK DIAGRAM
PLL1
SSC
EasyN
Programming
CPU CLK
Output Buffers
CPU[1:0]
X1
XTAL
Osc Amp
I
REF
REF 3.1.0
X2
PLL2
SSC
EasyN
Programming
SDATA
SCLK
SM Bus
Controller
3V66/PCI
Output Buffers
PCI[5:0], PCIF[2:0]
3V66[3:0]
PLL3
SSC
V
TT_PWRGD
Watch Dog
Timer
FS[1:0]
Control
Logic
SRC CLK
Output Buffer
SRC
I
REF
48MHz[1:0]
S
EL
24_48#
PLL4
48MHz
Output Buffer
24 - 48MHz
RESET#
OUTPUT TABLE
CPU (Pair)
2
3V66
3
3V66/VCH
1
PCI
6
PCIF
3
REF
3
48MHz
2
24 - 48MHz
1
SRC (Pair)
1
Reset#
1
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
漏 2003 Integrated Device Technology, Inc.
SEPTEMBER 2003
DSC-6382/16

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