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IDTCSPU877ANL Datasheet

  • IDTCSPU877ANL

  • 1.8V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER

  • 13頁(yè)

  • IDT

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IDTCSPU877A
1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
1.8V PHASE LOCKED LOOP
DIFFERENTIAL 1:10 SDRAM
CLOCK DRIVER
FEATURES:
DESCRIPTION:
IDTCSPU877A
鈥?1 to 10 differential clock distribution
鈥?Optimized for clock distribution in DDR2 (Double Data Rate)
SDRAM applications
鈥?Operating frequency: 125MHz to 270MHz
鈥?Very low skew:
鈮?/div>
40ps
鈥?Very low jitter:
鈮?/div>
40ps
鈥?1.8V AV
DD
and 1.8V V
DDQ
鈥?CMOS control signal input
鈥?Test mode enables buffers while disabling PLL
鈥?Low current power-down mode
鈥?Tolerant of Spread Spectrum input clock
鈥?Available in 52-Ball VFBGA and 40-pin MLF packages
APPLICATIONS:
鈥?Meets or exceeds JEDEC standard 82.8 for registered DDR2
clock driver
鈥?Along with SSTU32864/65/66, DDR2 register, provides complete
solution for DDR2 DIMMs
The CSPU877A is a PLL based clock driver that acts as a zero delay buffer
to distribute one differential clock input pair(CLK,
CLK
) to 10 differential
output pairs (Y
[0:9]
, Y
[0:9]
) and one differential pair of feedback clock output
(FBOUT,
FBOUT).
External feedback pins (FBIN,
FBIN)
for synchronization
of the outputs to the input reference is provided. OE, OS, and A
VDD
control the
power-down and test mode logic. When A
VDD
is grounded, the PLL is turned
off and bypassed for test mode purposes. When the differential clock inputs
(CLK,
CLK)
are both at logic low, this device will enter a low power-down mode.
In this mode, the receivers are disabled, the PLL is turned off, and the output
clock drivers are disabled, resulting in a current consumption device of less than
500碌A(chǔ).
The CSPU877A requires no external components and has been optimised
for very low phase error, skew, and jitter, while maintaining frequency and duty
cycle over the operating voltage and temperature range. The CSPU877A,
designed for use in both module assemblies and system motherboard based
solutions, provides an optimum high-performance clock source.
The CSPU877A is available in Commercial Temperature Range (0擄C to
+70擄C). See Ordering Information for details.
FUNCTIONAL BLOCK DIAGRAM
OE
OS
AV
DD
LD or OE
POWER
DOWN
AND
LD, OS, or OE
TEST
MODE
PLL BYPASS
LOGIC
LD
Y0
Y0
Y1
Y1
Y2
Y2
Y3
Y3
Y4
Y4
CLK
CLK
10K鈩?- 100K鈩?/div>
FBIN
FBIN
PLL
Y5
Y5
Y6
Y6
Y7
Y7
Y8
Y8
Y9
NOTE:
The Logic Detect (LD) powers down the device when a logic LOW is applied to both CLK and
CLK.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Y9
FBOUT
FBOUT
COMMERCIAL TEMPERATURE RANGE
1
c
2004
Integrated Device Technology, Inc.
JANUARY 2004
DSC-6495/4

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