IDTCSP2510D
3.3V PHASE-LOCK LOOP CLOCK DRIVER
0
擄
C TO 85
擄
C TEMPERATURE RANGE
3.3V PHASE-LOCK LOOP
CLOCK DRIVER
ZERO DELAY BUFFER
FEATURES:
DESCRIPTION:
鈥?Phase-Lock Loop Clock Distribution for Synchronous DRAM
Applications
鈥?Distributes one clock input to one bank of ten outputs
鈥?Output enable bank control
鈥?External feedback (FBIN) pin is used to synchronize the
outputs to the clock input signal
鈥?No external RC network required for PLL loop stability
鈥?Operates at 3.3V V
DD
鈥?tpd Phase Error at 166MHz: < 鹵150ps
鈥?Jitter (peak-to-peak) at 166MHz: < 鹵75ps @ 166MHz
鈥?Spread Spectrum Compatible
鈥?Operating frequency 50MHz to 175MHz
鈥?Available in 24-Pin TSSOP package
IDTCSP2510D
APPLICATIONS:
鈥?SDRAM Modules
鈥?PC Motherboards
鈥?Workstations
The CSP2510D is a high performance, low-skew, low-jitter, phase-lock
loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency
and phase, the feedback (FBOUT) output to the clock (CLK) input signal.
It is specifically designed for use with synchronous DRAMs. The CSP2510D
operates at 3.3V.
One bank of ten outputs provide low-skew, low-jitter copies of CLK.
Output signal duty cycles are adjusted to 50 percent, independent of the duty
cycle at CLK. The outputs can be enabled or disabled via the control G input.
When the G input is high, the outputs switch in phase and frequency with
CLK; when the G input is low, the outputs are disabled to the logic-low state.
Unlike many products containing PLLs, the CSP2510D does not require
external RC networks. The loop filter for the PLL is included on-chip,
minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CSP2510D requires a
stabilization time to achieve phase lock of the feedback signal to the
reference signal. This stabilization time is required, following power up and
application of a fixed-frequency, fixed-phase signal at CLK, as well as
following any changes to the PLL reference or feedback signals. The PLL
can be bypassed for the test purposes by strapping AV
DD
to ground.
The CSP2510D is specified for operation from 0擄C to +85擄C. This device
is also available (on special order) in Industrial temperature range (-40擄C
to +85擄C). See ordering information for details.
FUNCTIONAL BLOCK DIAGRAM
11
G
3
Y0
4
Y1
5
Y2
8
Y3
9
Y4
15
Y5
16
Y6
17
CLK
24
PLL
13
FBIN
21
AV
DD
23
12
FBOUT
Y9
20
Y8
Y7
潞
潞
0潞C TO 85潞C TEMPERATURE RANGE
1
c
2001 Integrated Device Technology, Inc.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
OCTOBER 2001
DSC-5874/2
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