T1/E1/OC3 WAN PLL WITH
DUAL REFERENCE INPUTS
FEATURES
鈥?Supports AT&T TR62411 and Telcordia GR-1244-CORE Stratum
3, Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces
鈥?Supports ITU-T G.813 Option 1 clocks
鈥?Supports ITU-T G.812 Type IV clocks
鈥?Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing
for E1 interface
鈥?Selectable reference inputs: 8 kHz, 1.544 MHz, 2.048 MHz or
19.44 MHz
鈥?Accepts two independent reference inputs which may have
same or different nominal frequencies applied to them
鈥?Provides C1.5o,
C3o,
C2o,
C4o,
C6o, C8o,
C16o,
C19o and
C32o
output clock signals
鈥?Provides 7 types of 8 kHz framing pulses:
F0o,
F8o,
F16o,
F19o,
F32o,
RSP and TSP
IDT82V3012
鈥?Provides a C2/C1.5 output clock signal with the frequency
controlled by the selected reference input Fref0 or Fref1
鈥?Holdover frequency accuracy of 0.025 ppm
鈥?Phase slope of 5 ns per 125 碌s
鈥?Attenuates wander from 2.1 Hz
鈥?Fast lock mode
鈥?Provides Time Interval Error (TIE) correction
鈥?MTIE of 600 ns
鈥?JTAG boundary scan
鈥?Holdover status indication
鈥?Freerun status indication
鈥?Normal status indication
鈥?Lock status indication
鈥?Input reference quality indication
鈥?3.3 V operation with 5 V tolerant I/O
鈥?Package available: 56-pin SSOP
FUNCTIONAL BLOCK DIAGRAM
TDO
TDI
OSCi
TCLR
RST
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
C2/C1.5
TCK
TMS
TRST
Fref0
Fref1
IN_sel
FLOCK
DPLL
JTAG
OSC
C32o
C19o
C19POS
C19NEG
TIE Control
Block
Virtual
Reference
Reference Input
Switch
C16o
C8o
C4o
C2o
C3o
C1.5o
C6o
F0o
F8o
F16o
F19o
F32o
RSP
TSP
LOCK
Frequency
Select Circuit 0
MON_out0
Reference Input
Monitor 0
Reference Input
Monitor 1
Feedback Signal
MON_out1
Invalid Input
Signal Detection
F0_sel0
F0_sel1
State Control Circuit
Frequency
Select Circuit 1
F1_sel0
F1_sel1
TIE_en MODE_sel1 MODE_sel0 Normal Holdover Freerun
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
錚?003
Integrated Device Technology, Inc.
OCTOBER 22, 2003
DSC-6238/3