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IDT79RC32V332-133DP Datasheet

  • IDT79RC32V332-133DP

  • MICROPROCESSOR|32-BIT|QFP|208PIN|PLASTIC

  • 26頁(yè)

  • ETC

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RISCore
TM
32300 Family
Integrated Processor
79RC32332
x
x
RC32300 32-bit Microprocessor
鈥?Up to 133 MHz operation
鈥?Enhanced MIPS-II Instruction Set Architecture (ISA)
鈥?Cache prefetch instruction
鈥?Conditional move instruction
鈥?DSP instructions
鈥?Supports big or little endian operation
鈥?MMU with 32 page TLB
鈥?8kB Instruction Cache, 2-way set associative
鈥?2kB Data Cache, 2-way set associative
鈥?Cache locking per line
鈥?Programmable on a page basis to implement a write-through
no write allocate, write-through write allocate, or write-back
algorithms for cache management
鈥?Compatible with a wide variety of operating systems
x
Local Bus Interface
鈥?Up to 66 MHz operation
鈥?23-bit address bus
鈥?32-bit data bus
鈥?Direct control of local memory and peripherals
鈥?Programmable system watch-dog timers
鈥?Big or little endian support
x
Interrupt Controller simplifies exception management
x
Four general purpose 32-bit timer/counters
Programmable I/O (PIO)
鈥?Input/Output/Interrupt source
鈥?Individually programmable
x
SDRAM Controller (32-bit memory only)
鈥?4 banks, non-interleaved
鈥?Up to 256MB total SDRAM memory supported
鈥?Implements full, direct control of discrete, SODIMM, or DIMM
memories
鈥?Supports 16Mb through 256Mb SDRAM device depths
鈥?Automatic refresh generation
x
Serial Peripheral Interface (SPI) master mode interface
x
UART Interface
鈥?16550 compatible UART
鈥?Baud rate support up to 1.5M
x
Memory & Peripheral Controller
鈥?6 banks, up to 8MB per bank
鈥?Supports 8-,16-, and 32-bit interfaces
鈥?Supports Flash ROM, SRAM, dual-port memory, and
peripheral devices
鈥?Supports external wait-state generation
鈥?8-bit boot PROM support
鈥?Flexible I/O timing protocols
PDUJDL' NFRO%
PDUJDL' NFRO%
PDUJDL' NFRO%
PDUJDL' NFRO%
錚?/div>
2001 Integrated Device Technology, Inc.
VHUXWDH)
VHUXWDH)
VHUXWDH)
VHUXWDH)
EJTAG
In-Circuit Emulator Interface
RISCore 32300
Enhanced M IPS-II ISA
Integer CPU
RC5000
Com patible
CP0
32-page
TLB
Interrupt Control
Program m able I/O
32-bit Tim ers
SPI C ontrol
DM A C ontrol
Local
M em ory/IO
Control
UART
IPBus
Bridge
2kB
2-set, Lockable
Data Cache
8 kB
2-set
Lockable
Instr. Cache
IDT
P eripheral
B us
S DRA M
C ontrol
P CI Bridge
Figure 1 RC32332 Block Diagram
1 of 26
March 13, 2001
DSC 5914

IDT79RC32V332-133DP相關(guān)型號(hào)PDF文件下載

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