Low-Cost Embedded
64-bit RISController
w/ DSP Capability
Features
High-performance embedded 64-bit microprocessor
鈥?64-bit integer operations
鈥?64-bit registers
鈥?Based on the MIPS RISC Architecture
鈥?100MHz, 133MHz, 150MHz, 180MHz, 200MHz and 267MHz
operating frequencies
鈥?32-bit bus interface brings 64-bit power to 32-bit system cost
x
High-performance DSP capability
鈥?133.5 Million Integer Mul-Accumulate
operations/sec @267MHz
鈥?89 MFlops floating-point operations @267MHz
x
High-performance microprocessor
鈥?133.5 M Mul-Add/second @267MHz
鈥?89 MFlops @267MHz
鈥?>640,000 dhrystone (2.1)/sec capability @267MHz (352
dhrystone MIPS)
x
High level of integration
鈥?64-bit, 267 MHz integer CPU
鈥?8KB instruction cache; 8KB data cache
鈥?Integer multiply unit with 133.5M Mul-Add/sec
x
Upwardly software compatible with IDT RISController
Family
x
Easily upgradable to 64-bit system
x
x
IDT79RC4640
鈩?/div>
Low-power operation
鈥?Active power management powers-down inactive units
鈥?Standby mode
x
Large, efficient on-chip caches
鈥?Separate 8KB Instruction and 8KB Data caches
鈥?Over 3200MB/sec bandwidth from internal caches
鈥?2-set associative
鈥?Write-back and write-through support
鈥?Cache locking, to facilitate deterministic response
鈥?High performance write protocols, for graphics and data
communications
x
Bus compatible with RC4000 family
鈥?System interfaces to 125MHz, provides bandwidth up to 500
MB/sec
鈥?Direct interface to 32-bit wide systems
鈥?Synchronized to external reference clock for multi- master
operation
鈥?Socket compatible with IDT RC 64474 and RC64574
x
Improved real-time support
鈥?Fast interrupt decode
鈥?Optional cache locking
Note:
鈥淩鈥?refers to 5V parts; 鈥淩V鈥?refers to 3.3V parts; 鈥淩C鈥?/div>
refers to both
Block Diagram
267 MHz 64-bit CPU
64-bit Register File
64-bit Adder
System Control Coprocessor
Address Translation/
Cache Attribute Control
89 MFlops Single-Precision FPA
FP Register File
Pipeline Control
Pipeline Control
Pack/Unpack
Load Aligner
Store Aligner
Logic Unit
High-Performance
Integer Multiply
Exception Management
Functions
FP Add/Sub/Cvt/
Div/Sqrt
FP Multiply
Control Bus
Data Bus
Instruction Bus
Instruction Cache
Set A
(Lockable)
32-bit
Synchronized
System Interface
Data Cache
Set A
(Lockable)
Data Cache
Set B
Instruction Cache
Set B
The IDT logo is a registered trademark and RC4600, RC4650, RC3081,RC3052,RC3051,RC3041 RISController, and RISCore are trademarks of Integrated Device Technology, Inc.
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錚?/div>
2001 Integrated Device Technology, Inc.
April 10, 2001
DSC 3486/2
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