鈥?/div>
鈥?On-chip DMA arbiter
鈥?Bus Interface minimizes design complexity
Single clock input with 40%-60% duty cycle
35 MIPS, over 64,000 Dhrystones at 40MHz
Low-cost 84-pin PLCC packaging that's pin-/package-
compatible with thermally enhanced 84-pin MQUAD.
Flexible bus interface allows simple, low-cost designs
20, 25, 33, and 40MHz operation
Complete software support
鈥?Optimizing compilers
鈥?Real-time operating systems
鈥?Monitors/debuggers
鈥?Floating Point Software
鈥?Page Description Languages
Clk2xIn
Clock
Generator
Unit
Master Pipeline Control
System Control
Coprocessor
Exception/Control
Registers
Memory Management
Registers
BrCond(3:0)
Integer
CPU Core
General Registers
(32 x 32)
ALU
Shifter
Int(5:0)
Translation
Lookaside Buffer
(64 entries)
Mult/Div Unit
Address Adder
PC Control
Virtual Address
32
Physical Address Bus
Instruction
Cache
(8kB/4kB)
Data Bus
Bus Interface Unit
4-deep
Write
Buffer
4-deep
Read
Buffer
DMA
Arbiter
Data
Cache
(2kB)
32
BIU
Control
Address/
Data
DMA
Ctrl
Rd/Wr
Ctrl
SysClk
2874 drw 01
Figure 1. R3051 Family Block Diagram
The IDT logo is a registered trademark, and RISChipset, RISController, R3041, R3051, R3052, R3071, R3081, R3720, R4400 and R4600 are trademarks of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
漏1995
Integrated Device Technology, Inc.
SEPTEMBER 1995
5.3
DSC-3000/5
1