SwitchStar
TM
ATM Cell Based
8 x 8 1.2Gbps non-blocking
Integrated Switching Memory
Features List
Single chip supports an 8 x 8 port switch at 155Mbps per
port
!
Central Memory Architecture eliminates Head-of-Line
Blocking by sharing the memory array with all ports
!
Low power dissipation
鈥?330mW (typ.)
!
Data Path Interface (DPI) provides configurable Input and
Output ports; up to 8 receive and 8 transmit ports at
155Mbps
!
Supports data rates up to 1.2Gbps with a 32-bit wide port
configuration; 155Mbps per 4-bit port
!
Can be cascaded for larger switch configurations
!
Fast Input/Output port cycle times
!
Expander and Concentrator function is fully supported by
the Input and Output port configuration options
!
8192 cells (52 to 56 bytes each) of on-chip buffer memory
capacity
!
!
IDT77V400
!
!
!
!
!
!
!
!
Configurable cell lengths of 52, 53, 54, 55, or 56 bytes can
be independently chosen for Input and Output ports
Byte Addition or Byte Subtraction for x4/x8 to x16/x32
conversion capability
Internal header Cyclical Redundancy Check (CRC) and
generation logic on-chip
Header modification, pre-pend, and post-pend operations
available as well as Multicasting and Broadcasting
capability
High-bandwidth control port for queue controller system
block, up to 36 MHz cycle time
Can be used with the companion IDT77V500 Switch
Controller or custom logic for traffic management
Industrial temperature range (-40擄C to +85擄C) is available
Single +3.3V 鹵 300mV power supply
Available in an 208-pin Plastic Quad Flat Pack (PQFP) and
256-ball BGA
Block Diagram
External Interface
for Global Setup
and Control
8-bit Processor/
Call Setup
Manager
or IDT77V550
Data
Control
IDT77V500
Switch
Controller
Data
Control
155Mbps
PHY
Port 0
Port 0
155Mbps
PHY
,
IDT77V400
Switching
Memory
155Mbps
PHY
Port 7
Port 7
155Mbps
PHY
3606 drw 01
Figure 1 Typical 8x8 Switch Configuration using the IDT77V400 Switching Memory
SwitchStar and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
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2001 Integrated Device Technology, Inc.
March 31, 2001
DSC 3606/6
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