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IDT77V1254L25L25PG Datasheet

  • IDT77V1254L25L25PG

  • Quad Port PHY (Physical Layer) for 25.6 and 51.2 ATM Network...

  • 47頁

  • IDT

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Quad Port PHY (Physical Layer)
for 25.6 and 51.2
ATM Networks
Features List
Performs the PHY-Transmission Convergence (TC) and
Physical Media Dependent (PMD) Sublayer functions for
four 25.6 Mbps ATM channels
Compliant to ATM Forum (af-phy-040.000) and ITU-T I.432.5
specifications for 25.6 Mbps physical interface
Also operates at 51.2 Mbps data rate
UTOPIA Level 1, UTOPIA Level 2, or DPI-4 Interface
3-Cell Transmit & Receive FIFOs
LED Interface for status signalling
Supports UTP Category 3 and 5 physical media
Interfaces to standard magnetics
Low-Power CMOS
3.3V supply with 5V tolerant inputs
144-pin PQFP Package (28 x 28 mm)
Commercial and Industrial Temperature Ranges
IDT77V1254L25
Description
The IDT77V1254L25 is a member of IDT's family of products
supporting Asynchronous Transfer Mode (ATM) data communications
and networking. The IDT77V1254L25 implements the physical layer for
25.6 Mbps ATM, connecting four serial copper links (UTP Category 3
and 5) to one ATM layer device such as a SAR or a switch ASIC. The
IDT77V1254L25 also operates at 51.2 Mbps, and is well suited to back-
plane driving applications.
The 77V1254L25-to-ATM layer interface is selectable as one of three
options: 16-bit UTOPIA Level 2, 8-bit UTOPIA Level 1 Multi-PHY, or
quadruple 4-bit DPI (Data Path Interface).
The IDT77V1254L25 is fabricated using IDT's state-of-the-art CMOS
technology, providing the highest levels of integration, performance and
reliability, with the low-power consumption characteristics of CMOS.
Block Diagram
TXREF
T X C LK
T X D A T A [15:0]
T X P A R IT Y
TX S O C
TXEN
T X C LA V
T X A D D R [4:0]
M O D E [1:0]
P H Y -A T M
Interface
(U T O P IA or D P I)
D ri
ver
T X /R X A T M
C el IF O
lF
S cram bl
er/
D escram bl
er
5B /4B
E ncodi
ng/
D ecodi
ng
P /S and S /P
N R ZI
+
Tx 1
-
+
Rx1
-
D ri
ver
T X /R X A T M
C el IF O
lF
S cram bl
er/
D escram bl
er
5B /4B
E ncodi
ng/
D ecodi
ng
P /S and S /P
N R ZI
+
TX 0
-
+
RX 0
-
C l R ecovery
ock
R X A D D R [4:0]
R X C LK
R X D A T A [15:0]
R X P A R IT Y
R XSO C
RXEN
R X C LA V
C l R ecovery
ock
INT
RST
D ri
ver
T X /R X A T M
C el IF O
lF
Mi
croprocessor
Interface
S cram bl
er/
D escram bl
er
5B /4B
E ncodi
ng/
D ecodi
ng
P /S and S /P
N R ZI
C l R ecovery
ock
+
- TX 2
+
-RX 2
RD
WR
CS
A D [7:0]
A LE
T X /R X A T M
C el IF O
lF
O SC
S cram bl
er/
D escram bl
er
5B /4B
E ncodi
ng/
D ecodi
ng
P /S and S /P
N R ZI
D ri
ver
+
- TX 3
+
-RX 3
C l R ecovery
ock
4
4
RXREF
R X LE D [3:0]
T X LE D [3:0]
35 0 5 drw 0 1
.
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
1 of 47
錚?/div>
2001 Integrated Device Technology, Inc.
September 21, 2001
DSC 6003

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