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IDT77V1254L25PGI Datasheet

  • IDT77V1254L25PGI

  • ATM Processor

  • 40頁

  • ETC

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Quad Port PHY (Physical Layer)
for 25.6 and 51.2
ATM Networks
IDT77V1254L25
Performs the PHY-Transmission Convergence (TC) and
Physical Media Dependent (PMD) Sublayer functions for
four 25.6 Mbps ATM channels
Compliant to ATM Forum (af-phy-040.000) and ITU-T I.432.5
specifications for 25.6 Mbps physical interface
Also operates at 51.2 Mbps
UTOPIA Level 1, UTOPIA Level 2, or DPI-4 Interface
3-Cell Transmit & Receive FIFOs
LED Interface for status signalling
Supports UTP Category 3 physical media
Interfaces to standard magnetics
Low-Power CMOS
3.3V supply with 5V tolerant inputs
144-pin PQFP Package (28 x 28 mm)
Commercial and Industrial Temperature Ranges
The IDT77V1254 is a member of IDT's family of products supporting
Asynchronous Transfer Mode (ATM) data communications and
networking. The IDT77V1254 implements the physical layer for 25.6
Mbps ATM, connecting four serial copper links (UTP Category 3) to one
ATM layer device such as a SAR or a switch ASIC. The IDT77V1254
also operates at 51.2 Mbps, and is well suited to backplane driving appli-
cations.
The 77V1254-to-ATM layer interface is selectable as one of three
options: 16-bit UTOPIA Level 2, 8-bit UTOPIA Level 1 Multi-PHY, or
quadruple 4-bit DPI (Data Path Interface).
The IDT77V1254 is fabricated using IDT's state-of-the-art CMOS
technology, providing the highest levels of integration, performance and
reliability, with the low-power consumption characteristics of CMOS.
TXREF
TXCLK
TXDATA[15:0]
TXPARITY
TXSOC
TXEN
TXCLAV
TXADDR[4:0]
MODE[1:0]
PHY-ATM
Interface
(UTOPIA or DPI)
TX/RX ATM
Cell FIFO
Scrambler/
Descrambler
RXADDR[4:0]
RXCLK
RXDATA[15:0]
RXPARITY
RXSOC
RXEN
RXCLAV
TX/RX ATM
Cell FIFO
Scrambler/
Descrambler
INT
RST
Microprocessor
Interface
RD
WR
CS
AD[7:0]
ALE
TX/RX ATM
Cell FIFO
Scrambler/
Descrambler
TX/RX ATM
Cell FIFO
OSC
Scrambler/
Descrambler
4
4
RXREF
RXLED[3:0]
1 of 40
錚?/div>
2001 Integrated Device Technology, Inc.
QRLWSLUFVH'
QRLWSLUFVH'
QRLWSLUFVH'
QRLWSLUFVH'
5B/4B
Encoding/
Decoding
5B/4B
Encoding/
Decoding
5B/4B
Encoding/
Decoding
5B/4B
Encoding/
Decoding
TXLED[3:0]
PDUJDL' NFRO%
PDUJDL' NFRO%
PDUJDL' NFRO%
PDUJDL' NFRO%
WVL/ VHUXWDH)
WVL/ VHUXWDH)
WVL/ VHUXWDH)
WVL/ VHUXWDH)
聥
聥
聥
聥
聥
聥
聥
聥
聥
聥
聥
聥
Driver
P/S and S/P
NRZI
Clock Recovery
+
TX 0
-
+
RX 0
-
Driver
P/S and S/P
NRZI
Clock Recovery
+
Tx 1
-
+
Rx 1
-
Driver
P/S and S/P
NRZI
Clock Recovery
+
- TX 2
+
- RX 2
Driver
P/S and S/P
NRZI
Clock Recovery
+
TX 3
-
+
RX 3
-
3505 drw 01
.
March 8, 2001
DSC 6003

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