鈥?/div>
IDT74LVCH16260A
bus multiplexer/transceiver for use in high-speed microprocessor applica-
tions. This bus exchanger supports memory interleaving with latched out-
puts on the B ports and address multiplexing with latched inputs on the B
ports.
The LVCH16260A tri-port bus exchanger has three 12-bit ports. Data
may be transferred between the A port and either/both of the B ports. The
latch enable (LE1B, LE2B, LEA1B and LEA2B) inputs control data storage.
When a latch-enable input is high, the latch is transparent. When a latch-
enable input is low, the data at the input is latched and remains latched until
the latch enable input is returned high. Independent output enables (OE1B
and
OE2B)
allow reading from one port while writing to the other port.
All pins of the 12-bit Bus Exchanger can be driven from either 3.3V or
5V devices. This feature allows the use of the device as a translator in a
mixed 3.3V/5V supply system.
The LVCH16260A has been designed with a 鹵24mA output driver. The
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
The LVCH16260A has 鈥渂us-hold鈥?which retains the inputs鈥?last state
whenever the input goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
APPLICATIONS:
鈥?5V and 3.3V mixed voltage systems
鈥?Data communication and telecommunication systems
DESCRIPTION:
The LVCH16260A tri-port bus exchanger is built using advanced dual
metal CMOS technology. The LVCH16260A is a high-speed 12-bit latched
Functional Block Diagram
OE1B
29
LEA1B
30
A-1B
LATCH
12
1B
1:12
LE1B
2
12
28
1
1B-A
LATCH
12
12
SEL
OEA
A
1:12
12
M
U
X
1
0
12
27
12
LE2B
2B-A
LATCH
12
55
LEA2B
56
A-2B
LATCH
2B
1:12
12
OE2B
EXTENDED COMMERCIAL TEMPERATURE RANGE
1
c
1999 Integrated Device Technology, Inc.
MARCH 1999
DSC-4229/1
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