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IDT74LVC125APG Datasheet

  • IDT74LVC125APG

  • 3.3V CMOS QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS AND...

  • 6頁

  • IDT

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IDT74LVC125A
3.3V CMOS QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS QUADRUPLE
BUS BUFFER GATE
WITH 3-STATE OUTPUTS
AND 5 VOLT TOLERANT I/O
鈥?0.5 MICRON CMOS Technology
鈥?ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
鈥?V
CC
= 3.3V 鹵 0.3V, Normal Range
鈥?V
CC
= 2.7V to 3.6V, Extended Range
鈥?CMOS power levels (0.4碌 W typ. static)
碌
鈥?Rail-to-Rail output swing for increased noise margin
鈥?All inputs, outputs, and I/Os are 5V tolerant
鈥?Supports hot insertion
鈥?Available in SOIC, SSOP, and TSSOP packages
IDT74LVC125A
FEATURES:
DESCRIPTION:
DRIVE FEATURES:
APPLICATIONS:
The LVC125A quadruple bus buffer gate is built using advanced dual
metal CMOS technology. The LVC125A features independent line drivers
with 3-state outputs. Each output is disabled when the associated output-
enable (OE) input is high.
To ensure the high impedance state during power up or power down,
OE
should be tied to Vcc through a pullup resistor; the minimum value of the
resistor is determined by the current-sinking capability of the driver.
Inputs can be driven from either 3.3V or 5V devices. This feature allows
the use of this device as a translator in a mixed 3.3V/5V system environment.
The LVC125A has been designed with a 鹵24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
鈥?High Output Drivers: 鹵24mA
鈥?Reduced system switching noise
鈥?5V and 3.3V mixed voltage systems
鈥?Data communication and telecommunication systems
FUNCTIONAL BLOCK DIAGRAM
1
OE
1
3
OE
10
1
A
2
3
1
Y
3
A
9
8
3
Y
2
OE
4
4
OE
13
2
A
5
6
2
Y
4
A
12
11
4
Y
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
漏2000 Integrated Device Technology, Inc.
FEBRUARY 2000
DSC-4557/1

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