鈮?/div>
1碌A(chǔ) (max.)
CMOS power levels
True TTL input and output compatibility:
鈥?V
OH
= 3.3V (typ.)
鈥?V
OL
= 0.3V (typ.)
High Drive outputs (-15mA I
OH
, 48mA I
OL
)
Meets or exceeds JEDEC standard 18 specifications
Power off disable outputs permit "live insertion"
Available in the SOIC and QSOP packages
IDT74FCT823AT/CT
DESCRIPTION:
The FCT823T series is built using an advanced dual metal CMOS
technology. The FCT823T series bus interface registers are designed to
eliminate the extra packages required to buffer existing registers and
provide extra data width for wider address/data paths or buses carrying
parity. The FCT823T is a 9-bit wide buffered register with Clock Enable
(EN) and Clear (CLR) 鈥?ideal for parity bus interfacing in high-performance
microprogrammed systems.
The FCT823T high-performance interface family can drive large capacitive
loads, while providing low-capacitance bus loading at both inputs and
outputs. All inputs have clamp diodes and all outputs are designed for low-
capacitance bus loading in high-impedance state.
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
FUNCTIONAL BLOCK DIAGRAM
D
0
EN
D
N
CLR
D
CL
Q
D
CL
Q
CP
Q
CP
Q
CP
OE
Y
0
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Y
N
INDUSTRIAL TEMPERATURE RANGE
1
JUNE 2006
DSC-5487/4
漏 2006 Integrated Device Technology, Inc.
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