Power off disable outputs permit 鈥渓ive insertion鈥?/div>
Typical V
OLP
(Output Ground Bounce) < 1.0V at V
CC
= 5V,
T
A
= 25擄C
鈥?Available in SSOP and TSSOP packages
DESCRIPTION:
The FCT16952T 16-bit registered transceiver is built using advanced
dual metal CMOS technology. These high-speed, low-power devices are
organized as two independent 8-bit D-type registered transceivers with
separate input and output control for independent control of data flow in either
direction. For example, the A-to-B Enable (xCEAB) must be low to enter
data from the A port. xCLKAB controls the clocking function. When xCLKAB
toggles from low-to-high, the data present on the A port will be clocked into
the register. xOEAB performs the output enable function on the B port. Data
flow from the B port to A port is similar but requires using xCEBA, xCLKBA,
and xOEBA inputs. Full 16-bit operation is achieved by tying the control pins
of the independent transceivers together.
The FCT16952T is ideally suited for driving high-capacitance loads and
low-impedance backplanes. The output buffers are designed with power off
disable capability allowing "live insertion" of boards when used as backplane
drivers.
FUNCTIONAL BLOCK DIAGRAM
54
31
1
CEBA
55
2
CEBA
30
1
CLKBA
1
2
CLKBA
28
1
OEAB
3
2
OEAB
26
1
CEAB
2
2
CEAB
27
1
CLKAB
56
2
CLKAB
29
1
OEBA
5
2
OEBA
C
CE
D
15
52
1
A
1
2
A
1
1
B
1
C
CE
D
42
2
B
1
C
CE
D
C
CE
D
TO SEVEN OTHER CHANNELS
TO SEVEN OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
2002 Integrated Device Technology, Inc.
JUNE 2002
DSC-5442/2
1
2
3
4
5
6
7
