Power off disable outputs permit 鈥渓ive insertion鈥?/div>
Typical V
OLP
(Output Ground Bounce) < 1.0V at V
CC
= 5V,
T
A
= 25擄C
Available in TSSOP package
IDT74FCT16501AT/CT
DESCRIPTION:
The FCT16501T 18-bit registered transceivers are built using advanced
dual metal CMOS technology. These high-speed, low-power 18-bit registered
bus transceivers combine D-type latches and D-type flip-flops to allow data flow
in transparent, latched and clocked modes. Data flow in each direction is
controlled by output-enable (OEAB and
OEBA),
latch enable (LEAB and LEBA)
and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device
operates in transparent mode when LEAB is high. When LEAB is low, the A data
is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A bus
data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. OEAB
is the output enable for the B port. Data flow from the B port to the A port is similar
but requires using
OEBA,
LEBA and CLKBA. Flow-through organization of
signal pins simplifies layout. All inputs are designed with hysteresis for improved
noise margin.
The FCT16501T are ideally suited for driving high-capacitance loads and
low-impedance backplanes. The output buffers are designed with power off
disable capability to allow "live insertion" of boards when used as backplane
drivers.
FUNCTIONAL BLOCK DIAGRAM
1
OEAB
30
CLKBA
28
LEBA
27
OEBA
CLKAB
LEAB
55
2
C
A
1
3
C
D
54
B
1
D
C
D
C
D
TO 17 OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
漏 2006 Integrated Device Technology, Inc.
june 2006
DSC-5435/4