鈭?/div>
0.5 MICRON CMOS Technology
Typical t
SK
(o) (Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
V
CC
= 3.3V 鹵0.3V, Normal Range or V
CC
= 2.7V to 3.6V, Extended
Range
CMOS power levels (0.4碌 W typ. static)
Rail-to-Rail output swing for increased noise margin
Low Ground Bounce (0.3V typ.)
Inputs (except I/O) can be driven by 3.3V or 5V components
Available in SSOP, TSSOP and TVSOP Packages
DESCRIPTION:
The FCT163344/A/C is a 1:4 address/clock driver built using advanced
dual metal CMOS technology. This high-speed, low power device provides
the ability to fanout to memory arrays. Eight banks, each with a fanout of
4, and 3-state control provide efficient address distribution. One or more
banks may be used for clock distribution.
The FCT163344/A/C have series current limiting resistors. These offer
low ground bounce, minimal undershoot and controlled output fall times,
reducing the need for external series terminating resistors.
A large number of power and ground pins ensure reduced noise levels.
All inputs are designed with hysteresis for improved noise margins.
The inputs of the FCT163344/A/C can be driven from either 3.3V or 5V
device. This feature allows the use of these devices as translators in a mixed
3.3V/5V supply system.
FUNCTIONAL BLOCK DIAGRAM
OE
1
1
2
8
6
OE
3
B
11
A
5
B
14
36
29
34
B
51
A
1
30
B
54
41
9
B
21
A
6
42
B
61
A
2
14
13
37
B
24
B
64
OE
2
28
16
OE
4
B
31
A
7
20
43
56
48
B
71
A
3
15
B
34
23
44
B
74
B
41
A
8
49
55
B
81
A
4
21
27
51
B
44
B
84
INDUSTRIAL TEMPERATURE RANGE
1
c
1999 Integrated Device Technology, Inc.
JUNE 2000
DSC-3249/-