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IDT74FCT16206CTPV Datasheet

  • IDT74FCT16206CTPV

  • BUS EXCHANGER|FCT/PCT-CMOS|SSOP|56PIN|PLASTIC

  • 8頁

  • ETC

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IDT74FCT16260AT/CT/ET
FAST CMOS 12-BIT TRI-PORT BUS EXCHANGER
INDUSTRIAL TEMPERATURE RANGE
FAST CMOS
12-BIT TRI-PORT
BUS EXCHANGER
FEATURES:
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
0.5 MICRON CMOS Technology
High-speed, low-power CMOS replacement for ABT functions
Typical t
SK(o)
(Output Skew) < 250ps
Low input and output leakage
鈮?/div>
1碌A(chǔ) (max.)
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
V
CC
= 5V 鹵10%
High drive outputs (鈥?2mA I
OH
, 64mA I
OL
)
Power off disable outputs permit 鈥渓ive insertion鈥?/div>
Typical V
OLP
(Output Ground Bounce) < 1.0V at V
CC
= 5V,
T
A
= 25擄C
Power off disable outputs permit 鈥渓ive insertion鈥?/div>
Available in SSOP and TSSOP packages
IDT74FCT16260AT/CT/ET
DESCRIPTION:
The FCT16260T Tri-Port Bus Exchangers are high-speed 12-bit latched
bus multiplexers/transceivers for use in high-speed microprocessor applica-
tions. These Bus Exchangers support memory interleaving with latched outputs
on the B ports and address multiplexing with latched inputs on the B ports.
The Tri-Port Bus Exchanger has three 12-bit ports. Data may be transferred
between the A port and either/both of the B ports. The latch enable (LE1B, LE2B,
LEA1B and LEA2B) inputs control data storage. When a latch-enable input is
high, the latch is transparent. When a latch-enable input is low, the data at the
input is latched and remains latched until the latch enable input is returned high.
Independent output enables (OE1B and
OE2B)
allow reading from one port
while writing to the other port.
The FCT16260T is ideally suited for driving high capacitance loads and low
impedance backplanes. The output buffers are designed with power off disable
capability to allow "live insertion" of boards when used as backplane drivers.
FUNCTIONAL BLOCK DIAGRAM
29
OE1B
30
LEA1B
A-1B
LATC H
12
1B
1:12
2
LE1B
12
28
1
12
1B-A
LATC H
12
SEL
OEA
A
1:12
12
M1
U
X 0
12
12
27
LE2B
2B-A
LATC H
12
55
LEA2B
56
A-2B
LATC H
12
2B
1:12
OE2B
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
漏 2002 Integrated Device Technology, Inc.
JANUARY 2002
DSC-5431/2

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