鈮?/div>
1碌A(chǔ) (max.)
CMOS power levels
True TTL input and output compatibility:
鈥?V
OH
= 3.3V (typ.)
鈥?V
OL
= 0.3V (typ.)
High Drive outputs (-15mA I
OH
, 48mA I
OL
)
Meets or exceeds JEDEC standard 18 specifications
Power off disable outputs permit "live insertion"
Available in SOIC and QSOP packages
IDT74FCT161AT/CT
DESCRIPTION:
The IDT74FCT161T is a high-speed synchronous modulo-16 binary
counter built using an advanced dual metal CMOS technology. It is
synchronously presettable for application in programmable dividers and
has two types of count enable inputs plus a terminal count output for versatility
in forming synchronous multi-stage counters. The IDT74FCT161T has
asynchronous Master Reset inputs that override all other inputs and force
the outputs low.
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
.UNCTIONAL BLOCK DIAGRAM
P
0
PE
P
1
P
2
P
3
CEP
CET
TC
CP
CP
CP
D CP
C
D
Q
D
Q
Q
0
DETAIL
A
DETAIL
A
DETAIL
A
3
0
DETAIL A
MR
Q
0
Q
1
Q
2
Q
3
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
漏 2002 Integrated Device Technology, Inc.
MARCH 2002
DSC-5504/2
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