IDT74ALVCHR16601
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 18-BIT UNIVERSAL
IDT74ALVCHR16601
BUS TRANSCEIVER WITH
3-STATE OUTPUTS
AND BUS-HOLD
鈥?0.5 MICRON CMOS Technology
鈥?Typical t
SK(o)
(Output Skew) < 250ps
鈥?ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
鈥?V
CC
= 3.3V 鹵 0.3V, Normal Range
鈥?V
CC
= 2.7V to 3.6V, Extended Range
鈥?V
CC
= 2.5V 鹵 0.2V
鈥?CMOS power levels (0.4碌 W typ. static)
碌
鈥?Rail-to-Rail output swing for increased noise margin
鈥?Available in TSSOP package
FEATURES:
DESCRIPTION:
This 18-bit universal bus transceiver is built using advanced dual metal
CMOS technology. The transceiver combines D-type latches and D-type
flip-flops to allow data flow in transparent, latched, and clocked modes.
Data flow in each direction is controlled by output-enable (OEAB and
OEBA),
latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA)
inputs. The clock can be controlled by the clock-enable (CLKENAB and
CLKENBA)
inputs. For A-to-B data flow, the device operates in the
transparent mode when LEAB is high. When LEAB is low, the A data is
latched if CLKAB is held at a high or low logic level. If LEAB is low, the data
is stored in the latch/flip-flop on the low-to-high transition of CLKAB. Output
enable
OEAB
is active low. When
OEAB
is low, the outputs are active. When
OEAB
is high, the outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B but uses
OEBA,
LEBA, CLKBA
and
CLKENBA.
The ALVCHR16601 has series resistors in the device output structure
which will significantly reduce line noise when used with light loads. This
driver has been designed to drive
鹵
12mA at the designated threshold levels.
The ALVCHR16601 has 鈥渂us-hold鈥?which retains the inputs鈥?last state
whenever the input goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
DRIVE FEATURES:
APPLICATIONS:
鈥?Balanced Output Drivers: 鹵12mA
鈥?Low Switching Noise
鈥?3.3V high speed systems
鈥?3.3V and lower voltage computing systems
FUNCTIONAL BLOCK DIAGRAM
OEAB
CLKENAB
CLKAB
LEAB
LEBA
CLKBA
CLKENBA
OEBA
A
1
1
56
55
2
28
30
29
27
CE
3
1D
C1
CLK
54
B
1
CE
1D
C1
CLK
TO 17 OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
漏 2004 Integrated Device Technology, Inc.
JANUARY 2004
DSC-4491/3
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