鈥?/div>
0.5 MICRON CMOS Technology
Typical t
SK
(o) (Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
V
CC
= 3.3V 鹵0.3V, Normal Range
V
CC
= 2.7V to 3.6V, Extended Range
V
CC
= 2.5V 鹵0.2V
CMOS power levels (0.4碌 W typ. static)
Rail-to-Rail output swing for increased noise margin
Available in SOIC, SSOP, QSOP, and TSSOP packages
IDT74ALVCH245
DESCRIPTION:
This octal bus transceiver is built using advanced dual metal CMOS
technology. The three-state controls are designed to operate this device
in a single-byte mode. All inputs are designed with hysteresis for improved
noise margin.
The ALVCH245 is designed for asynchronous communication between
data buses. The device transmits data from the A bus to the B bus or from
the B bus to the A bus, depending on the logic level at the direction-control
(DIR) input.
The ALVCH245 has been designed with a 鹵24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
The ALVCH245 has 鈥渂us-hold鈥?which retains the inputs鈥?last state
whenever the input bus goes to a high impedance. This prevents floating
inputs and eliminates the need for pull-up/down resistors.
Drive Features for ALVCH245:
鈥?High Output Drivers: 鹵24mA
鈥?Suitable for heavy loads
APPLICATIONS:
鈥?3.3V High Speed Systems
鈥?3.3V and lower voltage computing systems
FUNCTIONAL BLOCK DIAGRAM
DIR
1
19
OE
A
1
2
18
B
1
TO SEVEN OTHER CHANNELS
INDUSTRIAL TEMPERATURE RANGE
1
c
1999 Integrated Device Technology, Inc.
SEPTEMBER 2000
DSC-4471/-