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IDT74ALVCH16901PA Datasheet

  • IDT74ALVCH16901PA

  • 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY GENER...

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  • IDT

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IDT74ALVCH16901
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 18-BIT
IDT74ALVCH16901
UNIVERSAL BUS TRANSCEIVER
WITH PARITY GENERATORS/
CHECKERS AND BUS-HOLD
鈥?0.5 MICRON CMOS Technology
鈥?Typical t
SK(o)
(Output Skew) < 250ps
鈥?ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
鈥?V
CC
= 3.3V 鹵 0.3V, Normal Range
鈥?V
CC
= 2.7V to 3.6V, Extended Range
鈥?V
CC
= 2.5V 鹵 0.2V
鈥?CMOS power levels (0.4碌 W typ. static)
碌
鈥?Rail-to-Rail output swing for increased noise margin
鈥?Available in TSSOP package
FEATURES:
DESCRIPTION:
DRIVE FEATURES:
鈥?High Output Drivers: 鹵24mA
鈥?Suitable for heavy loads
APPLICATIONS:
鈥?3.3V high speed systems
鈥?3.3V and lower voltage computing systems
This 18-bit universal bus transceiver is built using advanced dual metal
CMOS technology. The ALVCH16901 is a dual 9-bit to dual 9-bit parity
transceiver with registers. The device can operate as a feed-through
transceiver or it can generate/check parity from the two 8-bit data buses in
either direction.
The ALVCH16901 features independent clock (CLKAB or CLKBA),
latch-enable (LEAB or LEBA), and dual 9-bit clock enable (CLKENAB or
CLKENBA)
inputs. It also provides parity-enable (SEL) and parity-select
(ODD/EVEN) inputs and separate error-signal (ERRA and
ERRB)
outputs
for checking parity. The direction of data flow is controlled by
OEAB
and
OEBA.
When
SEL
is low, the parity functions are enabled. When
SEL
is high,
the parity functions are disabled and the device acts as an 18-bit registered
transceiver.
The ALVCH16901 has been designed with a 鹵24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
The ALVCH16901 has 鈥渂us-hold鈥?which retains the inputs鈥?last state
whenever the input bus goes to a high impedance. This prevents floating
inputs and eliminates the need for pull-up/down resistors.
FUNCTIONAL BLOCK DIAGRAM
LEAB
1
CLKENAB
2
CLKENAB
2
1
32
3
30
2
CLKAB
OEAB
35
OEBA
1
A
1
-
1
A
8
1
APAR
1
ERRB
2
A
1
-
2
A
8
2
APAR
2
ERRB
28
36
5
61
18
A-Port
Parity
Generate
and
Check
B Data
18-Bit
Storage
18
Q
A
B-Port
Parity
Generate
and
Check
A Data
18
29
60
4
1
B
1
-
1
B
8
1
BPAR
1
ERRA
2
B
1
-
2
A
8
37
2
BPAR
2
ERRA
18
Q
B
18-Bit
Storage
ODD/EVEN
SEL
34
31
62
CLKBA
1
CLKENBA
2
CLKENBA
2
64
33
63
LEBA
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
漏2000 Integrated Device Technology, Inc.
JUNE 2000
DSC-4582/1

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