IDT74ALVCH162374
3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
INDUSTRIAL TEMPERATURE RANGE
IDT74ALVCH162374
3.3V CMOS 16-BIT EDGE-
TRIGGERED D-TYPE FLIP-
FLOP WITH 3-STATE OUTPUTS
AND BUS-HOLD
FEATURES:
鈥?0.5 MICRON CMOS Technology
鈥?Typical t
SK(o)
(Output Skew) < 250ps
鈥?ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
鈥?V
CC
= 3.3V 鹵 0.3V, Normal Range
鈥?V
CC
= 2.7V to 3.6V, Extended Range
鈥?V
CC
= 2.5V 鹵 0.2V
鈥?CMOS power levels (0.4渭 W typ. static)
渭
鈥?Rail-to-Rail output swing for increased noise margin
鈥?Available in TSSOP package
DESCRIPTION:
This 16-bit edge-triggered D-type flip-flop is built using advanced dual metal
CMOS technology. The ALVCH162374 is particularly suitable for implementing
buffer registers, I/O ports, bidirectional bus drivers, and working registers. It can
be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of
the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up
at the data (D) inputs.
OE
can be used to place the eight outputs in either a normal
logic state (high or low logic levels) or a high-impedance state. In the high-
impedance state, the outputs neither load nor drive the bus lines significantly.
The high-impedance state and the increased drive provide the capability to
drive bus lines without need for interface or pullup components.
OE
does not
affect internal operations of the flip-flop. Old data can be retained or new data
can be entered while the outputs are in the high-impedance state.
The ALVCH162374 has series resistors in the device output structure which
will significantly reduce line noise when used with light loads. This driver has
been designed to drive 鹵12mA at the designated threshold levels.
The ALVCH162374 has 鈥渂us-hold鈥?which retains the inputs鈥?last state
whenever the input goes to a high impedance. This prevents floating inputs and
eliminates the need for pull-up/down resistor.
DRIVE FEATURES:
鈥?Balanced Output Drivers: 鹵12mA
鈥?Low switching noise
APPLICATIONS:
鈥?3.3V high speed systems
鈥?3.3V and lower voltage computing systems
FUNCTIONAL BLOCK DIAGRAM
1
OE
1
2
OE
24
1
CLK
48
2
CLK
25
C1
2
C1
1
Q
1
2
D
1
36
13
2
Q
1
1
D
1
47
1D
1D
TO 7 OTHER CHANNELS
TO 7 OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
漏 1999 Integrated Device Technology, Inc.
MARCH 1999
DSC-4565/4
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