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IDT74ALVC162836PV Datasheet

  • IDT74ALVC162836PV

  • 20-Bit Buffer/Driver

  • 6頁

  • ETC

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IDT74ALVC162836
3.3V CMOS 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 20-BIT
UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
FEATURES:
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
0.5 MICRON CMOS Technology
Typical t
SK(0)
(Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
V
CC
= 3.3V 鹵 0.3V, Normal Range
V
CC
= 2.7V to 3.6V, Extended Range
V
CC
= 2.5V 鹵 0.2V
CMOS power levels (0.4碌 W typ. static)
Rail-to-Rail output swing for increased noise margin
Available in SSOP, TSSOP, and TVSOP packages
IDT74ALVC162836
DESCRIPTION:
This 20-bit universal bus driver is built using advanced dual metal CMOS
technology. Data flow from A to Y is controlled by the output-enable (OE)
input. The device operates in the transparent mode when the latch-enable
(LE) input is low. When
LE
is high, the A data is latched if the clock (CLK)
input is held at a high or low logic level. If
LE
is high, the A data is stored
in the latch/flip-flop on the low-to-high transition of CLK. When
OE
is high,
the outputs are in the high-impedance state.
The ALVC162836 has series resistors in the device output structure
which will significantly reduce line noise when used with light loads. This
driver has been designed to drive 鹵12mA at the designated threshold
levels.
Drive Features for ALVC162836:
鈥?Light Balanced Output Drivers: 鹵12mA
鈥?Minimal switching noise
APPLICATIONS:
鈥?/div>
SDRAM Modules
鈥?/div>
PC Motherboards
鈥?/div>
Workstations
FUNCTIONAL BLOCK DIAGRAM
OE
1
CLK
56
LE
29
A
1
55
1
D
2
C
1
CLK
Y
1
TO 19 OTHER CHANNELS
INDUSTRIAL TEMPERATURE RANGE
1
c
1999
Integrated Device Technology, Inc.
JULY 2001
DSC-4900/3

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