IDT74ALVC162268
3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 12-BIT TO
24-BIT REGISTERED BUS
EXCHANGER WITH
3-STATE OUTPUTS
FEATURES:
鈥?0.5 MICRON CMOS Technology
鈥?Typical t
SK(o)
(Output Skew) < 250ps
鈥?ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
鈥?V
CC
= 3.3V 鹵 0.3V, Normal Range
鈥?V
CC
= 2.7V to 3.6V, Extended Range
鈥?V
CC
= 2.5V 鹵 0.2V
鈥?CMOS power levels (0.4碌 W typ. static)
碌
鈥?Rail-to-Rail output swing for increased noise margin
鈥?Available in SSOP, TSSOP, and TVSOP packages
IDT74ALVC162268
DESCRIPTION:
This registered bus exchanger is built using advanced dual metal CMOS
technology. This device is used for applications in which data must be
transferred from a narrow high-speed bus to a wide, lower-frequency bus.
The ALVC162268 device provides synchronous data exchange be-
tween the two ports. Data is stored in the internal registers on the low-to-
high transition of the clock (CLK) input when the appropriate clock-enable
(CLKEN) inputs are low. The select (SEL) line is synchronous with CLK
and selects 1B or 2B input data for the A outputs. For data transfer in the
A-to-B direction, a two-stage pipeline is provided in the A-to-1B path, with
a single storage register in the A-to-2B path. Proper control of these inputs
allows two sequential 12-bit words to be presented synchronously as a 24-
bit word on the B-port. Data flow is controlled by the active-low output
enables (OEA and
OEB).
These control terminals are registered to
synchronize the bus-direction changes with CLK.
The ALVC162268 has series resistors in the device output structure of
the 鈥淏鈥?port which will significantly reduce line noise when used with light
loads. This driver has been designed to drive 鹵12mA at the designated
threshold levels. The 鈥淎鈥?port has a 鹵24mA driver.
DRIVE FEATURES:
鈥?High Output Drivers: 鹵24mA (A port)
鈥?Balanced Output Drivers: 鹵12mA (B port)
APPLICATIONS:
鈥?3.3V high speed systems
鈥?3.3V and lower voltage computing systems
FUNCTIONAL BLOCK DIAGRAM
CLK
29
2
CLKEN1B
27
CLKEN2B
30
CLKENA1
CLKENA2
OEB
55
C1
56
1D
C1
SEL
OEA
28
1D
1
1D
C1
CE
C1
1D
23
1
B
1
A1
8
0
1
CE
C1
1D
6
2
B
1
CE
C1
1D
CE
C1
1D
CE
C1
1D
1 of 12 Channels
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
漏 1999 Integrated Device Technology, Inc.
AUGUST 1999
DSC-4550/1
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