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IDT74ALVC10DC Datasheet

  • IDT74ALVC10DC

  • Triple 3-input NAND Gate

  • 5頁

  • ETC

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IDT74ALVC10
3.3V CMOS TRIPLE 3-INPUT POSITIVE-NAND GATE
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS
TRIPLE 3-INPUT
POSITIVE-NAND GATE
FEATURES:
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
0.5 MICRON CMOS Technology
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
V
CC
= 3.3V 鹵 0.3V, Normal Range
V
CC
= 2.7V to 3.6V, Extended Range
V
CC
= 2.5V 鹵 0.2V
CMOS power levels (0.4碌 W typ. static)
Rail-to-Rail output swing for increased noise margin
Available in SOIC, SSOP and TSSOP packages
IDT74ALVC10
DESCRIPTION:
This triple 3-input positive-NAND gate is built using advanced dual metal
CMOS technology. The ALVC10 performs the Boolean function
Y = A 鈥?B 鈥?C or Y =
A
+
B
+
C
in positive logic.
The ALVC10 has been designed with a 鹵24mA output driver. This driver
is capable of driving a moderate to heavy load while maintaining speed
performance.
Drive Features for ALVC10:
鈥?High Output Drivers: 鹵24mA
鈥?Suitable for heavy loads
APPLICATIONS:
鈥?/div>
3.3V High Speed Systems
鈥?/div>
3.3V and lower voltage computing systems
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
1
A
1
B
1
2
3
4
5
6
7
14
13
12
SO14-1
SO14-2 11
SO14-3
10
9
8
V
CC
1
C
1
Y
3
C
3
B
3
A
3
Y
A
B
C
Y
2
A
2
B
2
C
2
Y
GND
SOIC/ SSOP/ TSSOP
TOP VIEW
(1)
Output
xY
L
H
H
H
PIN DESCRIPTION
Pin Names
xA, xB, xC
xY
Description
Data Inputs
Data Outputs
FUNCTION TABLE
xA
H
L
X
X
Inputs
xB
H
X
L
X
(each gate)
xC
H
X
X
L
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
INDUSTRIAL TEMPERATURE RANGE
1
c
1999 Integrated Device Technology, Inc.
JUNE 2000
DSC-4634/-

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