鈮?/div>
1碌A(chǔ) (max.)
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
鈥?Bus Hold retains last active bus state during 3-state
鈥?Eliminates the need for external pull up resistors
鈥?Available in SSOP and TSSOP packages
The FCT162H501T 18-bit registered transceivers are built using advanced
dual metal CMOS technology. These high-speed, low-power 18-bit registered
bus transceivers combine D-type latches and D-type flip-flops to allow data flow
in transparent, latched and clocked modes. Data flow in each direction is
controlled by output-enable (OEAB and
OEBA),
latch enable (LEAB and LEBA)
and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates
in transparent mode when LEAB is high. When LEAB is low, the A data is latched
if CLKAB is held at a high or low logic level. If LEAB is low, the A bus data is
stored in the latch/flip-flop on the low-to-high transition of CLKAB. OEAB is the
output enable for the B port. Data flow from the B port to the A port is similar but
requires using
OEBA,
LEBA and CLKBA. Flow-through organization of signal
pins simplifies layout. All inputs are designed with hysteresis for improved noise
margin.
The FCT162H501T has "Bus Hold" which retains the input's last state
whenever the input goes to high impedance. This prevents "floating" inputs and
eliminates the need for pull-up/down resistors.
FUNCTIONAL BLOCK DIAGRAM
1
OEAB
30
CLKB A
28
LEBA
27
OEB A
CLKA B
LEAB
55
2
C
A
1
3
C
D
54
B
1
D
C
D
C
D
TO 17 OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
漏 2002 Integrated Device Technology, Inc.
NOVEMBER 2002
DSC-5434/1