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IDT72V83L20PA Datasheet

  • IDT72V83L20PA

  • 3.3 Volt CMOS DUAL ASYNCHRONOUS FIFO DUAL 512 x 9, DUAL 1,02...

  • 11頁(yè)

  • IDT

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3.3 Volt CMOS DUAL ASYNCHRONOUS FIFO
DUAL 512 x 9, DUAL 1,024 x 9
DUAL 2,048 x 9, DUAL 4,096 X 9
DUAL 8,192 X 9
IDT72V81
IDT72V82
IDT72V83
IDT72V84
IDT72V85
FEATURES:
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DESCRIPTION:
The IDT72V81/72V82/72V83/72V84/72V85 are dual-FIFO memories that
load and empty data on a first-in/first-out basis. These devices are functional and
compatible to two IDT72V01/72V02/72V03/72V04/72V05 FIFOs in a single
package with all associated control, data, and flag lines assigned to separate
pins. The devices use Full and Empty flags to prevent data overflow and
underflow and expansion logic to allow for unlimited expansion capability in both
word size and depth.
The reads and writes are internally sequential through the use of ring
pointers, with no address information required to load and unload data. Data
is toggled in and out of the devices through the use of the Write (W) and Read
(R) pins.
The devices utilize a 9-bit wide data array to allow for control and parity
bits at the user鈥檚 option. This feature is especially useful in data communications
applications where it is necessary to use a parity bit for transmission/reception
error checking. It also features a Retransmit (RT) capability that allows for reset
of the read pointer to its initial position when
RT
is pulsed low to allow for
retransmission from the beginning of data. A Half-Full Flag is available in the
single device mode and width expansion modes.
These FIFOs are fabricated using IDT鈥檚 high-speed CMOS technology.
They are designed for those applications requiring asynchronous and simul-
taneous read/writes in multiprocessing and rate buffer applications.
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The IDT72V81 is equivalent to two IDT72V01 - 512 x 9 FIFOs
The IDT72V82 is equivalent to two IDT72V02 - 1,024 x 9 FIFOs
The IDT72V83 is equivalent to two IDT72V03 - 2,048 x 9 FIFOs
The IDT72V84 is equivalent to two IDT72V04 - 4,096 x 9 FIFOs
The IDT72V85 is equivalent to two IDT72V05 - 8,192 x 9 FIFOs
Low power consumption
鈥?Active: 330 mW (max.)
鈥?Power-down: 18 mW (max.)
Ultra high speed鈥?5 ns access time
Asynchronous and simultaneous read and write
Offers optimal combination of data capacity, small foot print
and functional flexibility
Ideal for bidirectional, width expansion, depth expansion, bus-
matching, and data sorting applications
Status Flags: Empty, Half-Full, Full
Auto-retransmit capability
High-performance CEMOS鈩?technology
Space-saving TSSOP package
Industrial temperature range (鈥?0擄C to +85擄C) is available
FUNCTIONAL BLOCK DIAGRAM
DATA INPUTS
(DA
0
-DA
8
)
WA
WRITE
CONTROL
WRITE
POINTER
THREE-
STATE
BUFFERS
RSA
WB
WRITE
CONTROL
WRITE
POINTER
DATA INPUTS
(DB
0
-DB
8
)
RSB
RAM
ARRAY A
512 x 9
1,024 x 9
2,048 x 9
4,096 x 9
8,192 x 9
READ
POINTER
RAM
ARRAY A
512 x 9
1,024 x 9
2,048 x 9
4,096 x 9
8,192 x 9
READ
POINTER
THREE-
STATE
BUFFERS
RA
READ
CONTROL
FLAG
LOGIC
EXPANSION
LOGIC
RESET
LOGIC
READ
CONTROL
FLAG
LOGIC
EXPANSION
LOGIC
RESET
LOGIC
XIA
XOA/HFA
FFA
EFA
DATA
OUTPUTS
(QA
0
-QA
8
)
FLA/RTA
RB
XIB
XOB/HFB
FFB
EFB
DATA
OUTPUTS
(QB
0
-QB
8
)
FLB/RTB
3966 drw 01
August 1999
1
1999
Integrated Device Technology, Inc.
DSC-3966/-

IDT72V83L20PA 產(chǎn)品屬性

  • 34

  • 集成電路 (IC)

  • 邏輯 - FIFO

  • 72V

  • 異步

  • 18.4K(1K x 18)

  • 33MHz

  • 20ns

  • 3 V ~ 3.6 V

  • 0°C ~ 70°C

  • 表面貼裝

  • 56-TFSOP(0.240",6.10mm 寬)

  • 56-TSSOP

  • 管件

  • 72V83L20PA

IDT72V83L20PA相關(guān)型號(hào)PDF文件下載

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