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IDT72V3686L15PF Datasheet

  • IDT72V3686L15PF

  • 3.3 VOLT CMOS TRIPLE BUS SyncFIFOTM WITH BUS-MATCHING

  • 39頁(yè)

  • IDT

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3.3 VOLT CMOS TRIPLE BUS SyncFIFO
TM
WITH BUS-MATCHING
16,384 x 36 x 2
32,768 x 36 x 2
65,536 x 36 x 2
IDT72V3686
IDT72V3696
IDT72V36106
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FEATURES
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Memory storage capacity:
IDT72V3686 鈥?16,384 x 36 x 2
IDT72V3696 鈥?32,768 x 36 x 2
IDT72V36106 鈥?65,536 x 36 x 2
Clock frequencies up to 100 MHz (6.5ns access time)
Two independent FIFOs buffer data between one bidirectional
36-bit port and two unidirectional 18-bit ports (Port C receives
and Port B transmits)
18-bit (word) and 9-bit (byte) bus sizing of 18 bits (word) on
Ports B and C
Select IDT Standard timing (using
EFA
,
EFB
,
FFA
, and
FFC
flag
functions) or First Word Fall Through Timing (using ORA, ORB,
IRA, and IRC flag functions)
Programmable Almost-Empty and Almost-Full flags; each has
five default offsets (8, 16, 64, 256 and 1024)
鈥?/div>
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Serial or parallel programming of partial flags
Big- or Little-Endian format for word and byte bus sizes
Loopback mode on Port A
Retransmit Capability
Master Reset clears data and configures FIFO, Partial Reset
clears data but retains configuration settings
Mailbox bypass registers for each FIFO
Free-running CLKA, CLKB and CLKC may be asynchronous or
coincident (simultaneous reading and writing of data on a single
clock edge is permitted)
Auto power down minimizes power dissipation
Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)
Pin compatible to the lower density parts, IDT72V3626/72V3636/
72V3646/72V3656/72V3666/72V3676
Industrial temperature range (鈥?0擄C to +85擄C) is available
擄
擄
FUNCTIONAL BLOCK DIAGRAM
MBF1
CLKA
CSA
W/RA
ENA
MBA
LOOP
MRS1
PRS1
Mail 1
Register
Output Bus-
Matching
Output
Register
Input
Register
Port-A
Control
Logic
18
B
0
-B
17
36
RAM ARRAY
16,384 x 36
32,768 x 36
65,536 x 36
36
FIFO1,
Mail1
Reset
Logic
36
Port-B
Control
Logic
Write
Pointer
Read
Pointer
CLKB
RENB
CSB
MBB
SIZEB
FFA/IRA
AFA
FS2
FS0/SD
FS1/SEN
A
0
-A
35
EFA/ORA
AEA
FIFO1
Status Flag
Logic
Common
Port
Control
Logic
(B and C)
EFB/ORB
AEB
Programmable Flag
Offset Registers
16
FIFO2
Timing
Mode
BE
Status Flag
Logic
Read
Pointer
Write
Pointer
FIFO2,
Mail2
Reset
Logic
Input Bus-
Matching
Input
Register
18
FWFT
FFC/IRC
AFC
MRS2
PRS2
36
RT1
RTM
RT2
Output
Register
FIFO1 and
FIFO2
Retransmit
Logic
36
RAM ARRAY
16,384 x 36
32,768 x 36
65,536 x 36
Mail 2
Register
36
C
0
-C
17
CLKC
WENC
MBC
SIZEC
4676 drw01
Port-C
Control
Logic
MBF2
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncFIFO餂?is a trademark of Integrated Device Technology, Inc.
COMMERICAL TEMPERATURE RANGE
錚?/div>
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
NOVEMBER 2003
1
DSC-4676/4

IDT72V3686L15PF 產(chǎn)品屬性

  • 36

  • 集成電路 (IC)

  • 邏輯 - FIFO

  • 72V

  • 同步

  • 1.1M（32K x 36）

  • 67MHz

  • 15ns

  • 3.15 V ~ 3.45 V

  • 0°C ~ 70°C

  • 表面貼裝

  • 128-LQFP

  • 128-TQFP（14x20）

  • 托盤(pán)

  • 72V3686L15PF

IDT72V3686L15PF相關(guān)型號(hào)PDF文件下載

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