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IDT72V3646L15PF Datasheet

  • IDT72V3646L15PF

  • 3.3 VOLT CMOS TRIPLE BUS SyncFIFO WITH BUS-MATCHING 256 x 36...

  • 36頁

  • IDT

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3.3 VOLT CMOS TRIPLE BUS
SyncFIFO
TM
WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2,
1,024 x 36 x 2
.EATURES:
鈥?/div>
IDT72V3626
IDT72V3636
IDT72V3646
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鈥?/div>
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Memory storage capacity:
IDT72V3626鈥?56 x 36 x 2
IDT72V3636鈥?12 x 36 x 2
IDT72V3646鈥?,024 x 36 x 2
Clock frequencies up to 100 MHz (6.5ns access time)
Two independent FIFOs buffer data between one bidirectional
36-bit port and two unidirectional 18-bit ports (Port C receives
and Port B transmits)
18-bit (word) and 9-bit (byte) bus sizing of 18 bits (word) on
Ports B and C
Select IDT Standard timing (using
EFA, EFB, FFA,
and
FFC
flag
functions) or First Word Fall Through Timing (using ORA, ORB,
IRA, and IRC flag functions)
Programmable Almost-Empty and Almost-Full flags; each has
鈥?/div>
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鈥?/div>
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鈥?/div>
鈥?/div>
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three default offsets (8, 16 and 64)
Serial or parallel programming of partial flags
Big- or Little-Endian format for word and byte bus sizes
Master Reset clears data and configures FIFO, Partial Reset
clears data but retains configuration settings
Mailbox bypass registers for each FIFO
Free-running CLKA, CLKB and CLKC may be asynchronous or
coincident (simultaneous reading and writing of data on a single
clock edge is permitted)
Auto power down minimizes power dissipation
Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)
Pin and functionally compatible versions of 5V operating
IDT723626/723636/723646
擄
擄
Industrial temperature range (鈥?0擄C to +85擄C) is available
.UNCTIONAL BLOCK DIAGRAM
MBF1
Mail 1
Register
Output Bus-
Matching
Input
Register
36
RAM ARRAY
256 x 36
512 x 36
1,024 x 36
36
Output
Register
CLKA
CSA
W/RA
ENA
MBA
MRS1
PRS1
Port-A
Control
Logic
18
B
0
-B
17
FIFO1,
Mail1
Reset
Logic
36
Port-B
Control
Logic
Write
Pointer
Read
Pointer
CLKB
RENB
CSB
MBB
SIZEB
FFA/IRA
AFA
SPM
FS0/SD
FS1/SEN
A
0
-A
35
EFA/ORA
AEA
FIFO1
Status Flag
Logic
Common
Port
Control
Logic
(B and C)
EFB/ORB
AEB
Programmable Flag
Offset Registers
10
FIFO2
Timing
Mode
BE
Status Flag
Logic
Read
Pointer
Write
Pointer
FIFO2,
Mail2
Reset
Logic
FWFT
FFC/IRC
AFC
MRS2
PRS2
36
Input
Register
36
RAM ARRAY
Input Bus-
Matching
Output
Register
256 x 36
512 x 36
1,024 x 36
Mail 2
Register
36
18
C
0
-C
17
CLKC
WENC
MBC
SIZEC
4665 drw01
Port-C
Control
Logic
MBF2
IDT, the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
AUGUST 2001
DSC-4665/4
1
錚?/div>
2001 Integrated Device Technology, Inc. All right reserved. Product specifications subject to change without notice.

IDT72V3646L15PF 產(chǎn)品屬性

  • 72

  • 集成電路 (IC)

  • 邏輯 - FIFO

  • 72V

  • 異步，同步

  • 72K（2K x 36）

  • 67MHz

  • 15ns

  • 3 V ~ 3.6 V

  • 0°C ~ 70°C

  • 表面貼裝

  • 128-LQFP

  • 128-TQFP（14x20）

  • 托盤

  • 72V3646L15PF

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