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IDT72V2111L20PF Datasheet

  • IDT72V2111L20PF

  • 3.3 VOLT HIGH DENSITY CMOS SUPERSYNC FIFO

  • 27頁

  • IDT

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3.3 VOLT HIGH DENSITY CMOS
SUPERSYNC FIFO鈩?/div>
262,144 x 9
524,288 x 9
.EATURES:
鈥?/div>
IDT72V2101
IDT72V2111
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Choose among the following memory organizations:
IDT72V2101
錚?/div>
262,144 x 9
IDT72V2111
錚?/div>
524,288 x 9
Pin-compatible with the IDT72V261/72V271 and the IDT72V281/
72V291 SuperSync FIFOs
10ns read/write cycle time (6.5ns access time)
Fixed, low first word data latency time
5V input tolerant
Auto power down minimizes standby power consumption
Master Reset clears entire FIFO
Partial Reset clears data, but retains programmable settings
Retransmit operation with fixed, low first word data latency time
Empty, Full and Half-Full flags signal FIFO status
Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of two preselected offsets
Program partial flags by either serial or parallel means
Select IDT Standard timing (using
EF
and
FF
flags) or First Word Fall
Through timing (using
OR
and
IR
flags)
Output enable puts data outputs into high impedance state
Easily expandable in depth and width
Independent Read and Write clocks (permit reading and writing
鈥?/div>
鈥?/div>
simultaneously)
Available in the 64-pin Thin Quad Flat Pack (TQFP)
High-performance submicron CMOS technology
DESCRIPTION:
The IDT72V2101/72V2111 are exceptionally deep, high speed, CMOS
First-In-First-Out (FIFO) memories with clocked read and write controls. These
FIFOs offer numerous improvements over previous SuperSync FIFOs,
including the following:
鈥?The limitation of the frequency of one clock input with respect to the other has
been removed. The Frequency Select pin (FS) has been removed, thus
it is no longer necessary to select which of the two clock inputs, RCLK or
WCLK, is running at the higher frequency.
鈥?The period required by the retransmit operation is now fixed and short.
鈥?The first word data latency period, from the time the first word is written to an
empty FIFO to the time it can be read, is now fixed and short. (The variable
clock cycle counting delay associated with the latency period found on
previous SuperSync devices has been eliminated on this SuperSync family.)
SuperSync FIFOs are particularly appropriate for network, video, telecommu-
nications, data communications and other applications that need to buffer large
amounts of data.
.UNCTIONAL BLOCK DIAGRAM
WEN
WCLK
D
0
-D
8
LD SEN
INPUT REGISTER
OFFSET REGISTER
FF/IR
PAF
EF/OR
PAE
HF
FWFT/SI
WRITE CONTROL
LOGIC
RAM ARRAY
262,144 x 9
524,288 x 9
FLAG
LOGIC
WRITE POINTER
READ POINTER
OUTPUT REGISTER
MRS
PRS
READ
CONTROL
LOGIC
RT
RESET
LOGIC
RCLK
REN
OE
Q
0
-Q
8
4669 drw 01
The SuperSync FIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
錚?/div>
2001 Integrated Device Technology, Inc.
MARCH 2001
DSC-4669/2

IDT72V2111L20PF 產品屬性

  • IDT72V2101/11

  • 45

  • 集成電路 (IC)

  • 邏輯 - FIFO

  • 72V

  • 同步

  • 4.6K（512 x 9）

  • -

  • 20ns

  • 3 V ~ 3.6 V

  • 0°C ~ 70°C

  • 表面貼裝

  • 64-LQFP

  • 64-TQFP（14x14）

  • 托盤

  • 72V2111L20PF

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