鈥?/div>
Master Reset clears entire FIFO
Partial Reset clears data, but retains programmable settings
Empty, Full and Half-Full flags signal FIFO status
Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of eight preselected offsets
Program programmable flags through serial input
Output enable puts data outputs into high impedance state
JTAG port, provided for Boundary Scan function (PBGA Only)
Available in a 80-pin (V-III) Thin Quad Flat Pack, 128-pin(Vx-III)
Thin Quad Flat Pack (TQFP) or a 144-pin (Vx-III) Plastic Ball Grid
Array (PBGA) (with additional features)
Industrial temperature range (鈥?0擄C to +85擄C)
擄
擄
High-performance submicron CMOS technology
FUNCTIONAL BLOCK DIAGRAM
*
Available on the Vx-III PBGA package only.
MRS
WCLK
WEN
PRS
RCLK
REN
OE
D0 - Dn
Data In
x16, x32
FIFO ARRAY
Q0 - Qn
Data Out
x16, x32
WRITE
CONTROL
RESET LOGIC
READ
CONTROL
*
*
**
*
TCK
TRST
TMS
TDI
TDO
JTAG CONTROL
(BOUNDARY
SCAN)
*
LD
SEN
SI
PFM
FLAG LOGIC
FSEL1
EF
FSEL0
HF
PAE
FF
PAF
6163 drw01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
錚?/div>
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
NOVEMBER 2003
DSC-6163/2
next