鈥?/div>
DESCRIPTION
The IDT72V11165/72V12165/72V13165/72V14165/72V15165 devices
are First-In, First-Out (FIFO) memories with clocked read and write controls.
These FIFOs have 16-bit input and output ports. The input port is controlled
by a free-running clock (WCLK), and an input enable pin (WEN). Data is written
into the Multimedia FIFO on every clock when
WEN
is asserted. The output port
is controlled by another clock pin (RCLK) and another enable pin (REN). The
Read Clock (RCLK) can be tied to the Write Clock for single clock operation or
the two clocks can run asynchronous of one another for dual-clock operation.
An Output Enable pin (OE) is provided on the read port for three-state control
of the output.
These Multimedia FIFOs support three fixed flags: Empty Flag (EF), Full
Flag (FF), and Half Full Flag (HF).
256 x 16-bit organization array (IDT72V11165)
512 x 16-bit organization array (IDT72V12165)
1,024 x 16-bit organization array (IDT72V13165)
2,048 x 16-bit organization array (IDT72V14165)
4,096 x 16-bit organization array (IDT72V15165)
15 ns read/write cycle time
5V input tolerant
Independent Read and Write Clocks
Empty/Full and Half-Full flag capability
Output enable puts output data bus in high-impedance state
Available in a 64-lead thin quad flatpack (10x10mm and 14x14mm
TQFP)
Industrial temperature range (鈥?0擄C to +85擄C)
擄
擄
FUNCTIONAL BLOCK DIAGRAM
WCLK
WEN
WRITE
CONTROL
READ
CONTROL
RCLK
REN
FIFO ARRAY
D
0
- D
15
Data In
x16
OE
Q
0
- Q
15
Data Out
x16
RESET LOGIC
FLAG OUTPUTS
RS
EF
HF
FF
6359 drw01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
錚?003
Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
NOVEMBER 2003
DSC-6359/2