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IDT72T3695L10BBI Datasheet

  • IDT72T3695L10BBI

  • 2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 36-BIT CONFIGURATIONS

  • 57頁

  • IDT

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2.5 VOLT HIGH-SPEED TeraSync
TM
FIFO 36-BIT CONFIGURATIONS
1,024 x 36, 2,048 x 36, 4,096 x 36,
8,192 x 36, 16,384 x 36, 32,768 x 36,
65,536 x 36, 131,072 x 36 and 262,144 x 36
IDT72T3645, IDT72T3655, IDT72T3665,
IDT72T3675, IDT72T3685, IDT72T3695,
IDT72T36105, IDT72T36115, IDT72T36125
FEATURES:
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Choose among the following memory organizations:
IDT72T3645
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1,024 x 36
IDT72T3655
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2,048 x 36
IDT72T3665
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4,096 x 36
IDT72T3675
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8,192 x 36
IDT72T3685
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16,384 x 36
IDT72T3695
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32,768 x 36
IDT72T36105
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65,536 x 36
IDT72T36115
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131,072 x 36
IDT72T36125
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262,144 x 36
Up to 225 MHz Operation of Clocks
User selectable HSTL/LVTTL Input and/or Output
2.5V LVTTL or 1.8V, 1.5V HSTL Port Selectable Input/Ouput voltage
3.3V Input tolerant
Read Enable & Read Clock Echo outputs aid high speed operation
User selectable Asynchronous read and/or write port timing
Mark & Retransmit, resets read pointer to user marked position
Write Chip Select (WCS) input enables/disables Write operations
Read Chip Select (RCS) synchronous to RCLK
Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of eight preselected offsets
Program programmable flags by either serial or parallel means
Selectable synchronous/asynchronous timing modes for Almost-
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Empty and Almost-Full flags
Separate SCLK input for Serial programming of flag offsets
User selectable input and output port bus-sizing
- x36 in to x36 out
- x36 in to x18 out
- x36 in to x9 out
- x18 in to x36 out
- x9 in to x36 out
Big-Endian/Little-Endian user selectable byte representation
Auto power down minimizes standby power consumption
Master Reset clears entire FIFO
Partial Reset clears data, but retains programmable settings
Empty, Full and Half-Full flags signal FIFO status
Select IDT Standard timing (using
EF
and
FF
flags) or First Word
Fall Through timing (using
OR
and
IR
flags)
Output enable puts data outputs into high impedance state
JTAG port, provided for Boundary Scan function
Available in 208-pin (17mm x 17mm) or 240-pin (19mm x 19mm)
Plastic Ball Grid Array (PBGA)
Easily expandable in depth and width
Independent Read and Write Clocks (permit reading and writing
simultaneously)
High-performance submicron CMOS technology
Industrial temperature range (鈥?0擄C to +85擄C) is available
擄
擄
LD
SEN
SCLK
FUNCTIONAL BLOCK DIAGRAM
D
0
-D
n
(x36, x18 or x9)
WEN
WCLK/WR
WCS
INPUT REGISTER
OFFSET REGISTER
FF/IR
PAF
EF/OR
PAE
HF
FWFT/SI
PFM
FSEL0
FSEL1
ASYW
WRITE CONTROL
LOGIC
RAM ARRAY
1,024 x 36, 2,048 x 36
4,096 x 36, 8,192 x 36
16,384 x 36, 32,768 x 36
65,536 x 36, 131,072 x36
262,144 x 36
FLAG
LOGIC
WRITE POINTER
BE
IP
BM
IW
OW
MRS
PRS
TCK
TRST
TMS
TDO
TDI
Vref
WHSTL
RHSTL
SHSTL
CONTROL
LOGIC
BUS
CONFIGURATION
RESET
LOGIC
READ POINTER
OUTPUT REGISTER
READ
CONTROL
LOGIC
RT
MARK
ASYR
JTAG CONTROL
(BOUNDARY SCAN)
RCLK/RD
REN
RCS
HSTL I/0
CONTROL
OE
EREN
5907 drw01
Q
0
-Q
n
(x36, x18 or x9)
ERCLK
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The TeraSync FIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
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2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
SEPTEMBER 2003
DSC-5907/17

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