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IDT72413L35DB Datasheet

  • IDT72413L35DB

  • CMOS PARALLEL 64 x 5-BIT FIFO WITH FLAGS

  • 11頁

  • IDT

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CMOS PARALLEL
64 x 5-BIT FIFO
WITH FLAGS
Integrated Device Technology, Inc.
IDT72413
FEATURES:
鈥?First-ln/First-Out Dual-Port memory鈥?5MHz
鈥?64 x 5 organization
鈥?Low-power consumption
鈥?Active: 200mW (typical)
鈥?RAM-based internal structure allows for fast fall-through
time
鈥?Asynchronous and simultaneous read and write
鈥?Expandable by bit width
鈥?Cascadable by word depth
鈥?Half-Full and Almost-Full/Empty status flags
鈥?IDT72413 is pin and functionally compatible with the
MMI67413
鈥?High-speed data communications applications
鈥?Bidirectional and rate buffer applications
鈥?High-performance CMOS technology
鈥?Available in plastic DIP, CERDIP and SOIC
鈥?Military product compliant to MIL-STD-883, Class B
鈥?Industrial temperature range (-40
o
C to +85
o
C) is avail-
able, tested to military electrical specifications
DESCRIPTION:
The IDT72413 is a 64 x 5, high-speed First-In/First-Out
(FIFO) that loads and empties data on a first-in-first-out basis.
It is expandable in bit width. All speed versions are cascad-
able in depth.
The FIFO has a Half-Full Flag, which signals when it has 32
or more words in memory. The Almost-Full/Empty Flag is
active when there are 56 or more words in memory or when
there are 8 or less words in memory.
The IDT72413 is pin and functionally compatible to the
MMI67413. It operates at a shift rate of 45MHz. This makes it
ideal for use in high-speed data buffering applications. The
IDT72413 can be used as a rate buffer, between two digital
systems of varying data rates, in high-speed tape drivers, hard
disk controllers, data communications controllers and
graphics controllers.
The IDT72413 is fabricated using IDTs high-performance
CMOS process. This process maintains the speed and high
output drive capability of TTL circuits in low-power CMOS.
Military grade product is manufactured in compliance with
the latest revision of MIL-STD-883, Class B.
FUNCTIONAL BLOCK DIAGRAM
OUPUT ENABLE
(OE)
DATA
IN
(D
0-4
)
(MR)
MASTER
RESET
INPUT
READY
SHIFT
IN
(IR)
FIFO
INPUT
STAGE
64 x 5
MEMORY
ARRAY
FIFO
OUTPUT
STAGE
DATA
OUT
(Q
0-4
)
(SO)
INPUT
CONTROL
LOGIC
REGISTER
CONTROL
LOGIC
OUTPUT
CONTROL
LOGIC
(OR)
SHIFT
OUT
OUPUT
READY
(SI)
FLAG
CONTROL
LOGIC
HALF-FULL (HF)
ALMOST-FULL/
EMPTY (AF/E)
2748 drw 01
The IDT logo is a registered trademark of Integrated Device Technology,Inc.
FAST is a trademark of National Semiconductor, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
漏1996
Integrated Device Technology, Inc.
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
DECEMBER 1996
DSC-2748/7
5.02
1

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