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IDT72285L20TF Datasheet

  • IDT72285L20TF

  • x18 Synchronous FIFO

  • 26頁

  • ETC

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CMOS SuperSync FIFO鈩?/div>
32,768 x 18
65,536 x 18
.EATURES:
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
IDT72275
IDT72285
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Choose among the following memory organizations:
IDT72275
32,768 x 18
IDT72285
65,536 x 18
Pin-compatible with the IDT72255LA/72265LA SuperSync FIFOs
10ns read/write cycle time (6.5ns access time)
Fixed, low first word data latency time
Auto power down minimizes standby power consumption
Master Reset clears entire FIFO
Partial Reset clears data, but retains programmable
settings
Retransmit operation with fixed, low first word data
latency time
Empty, Full and Half-Full flags signal FIFO status
Programmable Almost-Empty and Almost-Full flags, each flag
can default to one of two preselected offsets
Program partial flags by either serial or parallel means
Select IDT Standard timing (using
EF
and
FF
flags) or First
Word Fall Through timing (using
OR
and
IR
flags)
Output enable puts data outputs into high impedance state
Easily expandable in depth and width
Independent Read and Write Clocks (permit reading and writing
simultaneously)
Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64-
pin Slim Thin Quad Flat Pack (STQFP)
High-performance submicron CMOS technology
Industrial temperature range (-40擄C to +85擄C) is available
DESCRIPTION:
The IDT72275/72285 are exceptionally deep, high speed, CMOS First-In-
First-Out (FIFO) memories with clocked read and write controls. These FIFOs
offer numerous improvements over previous SuperSync FIFOs, including the
following:
鈥?/div>
The limitation of the frequency of one clock input with respect to the other has
been removed. The Frequency Select pin (FS) has been removed, thus
it is no longer necessary to select which of the two clock inputs, RCLK or
WCLK, is running at the higher frequency.
鈥?/div>
The period required by the retransmit operation is now fixed and short.
鈥?/div>
The first word data latency period, from the time the first word is written to an
empty FIFO to the time it can be read, is now fixed and short. (The variable
clock cycle counting delay associated with the latency period found on
previous SuperSync devices has been eliminated on this SuperSync family.)
.UNCTIONAL BLOCK DIAGRAM
WEN
WCLK
D
0
-D
17
LD SEN
INPUT REGISTER
OFFSET REGISTER
FF/IR
PAF
EF/OR
PAE
HF
FWFT/SI
WRITE CONTROL
LOGIC
RAM ARRAY
32,768 x 18
65,536 x 18
FLAG
LOGIC
WRITE POINTER
READ POINTER
READ
CONTROL
LOGIC
OUTPUT REGISTER
MRS
PRS
RT
RESET
LOGIC
RCLK
REN
OE
Q
0
-Q
17
4674 drw 01
SuperSyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
漏 2001 Integrated Device Technology, Inc.
APRIL 2001
DSC-4674/1

IDT72285L20TF 產(chǎn)品屬性

  • IDT72275/85

  • 80

  • 集成電路 (IC)

  • 邏輯 - FIFO

  • 7200

  • 同步

  • 1.1M（65K x 18）

  • -

  • 20ns

  • 4.5 V ~ 5.5 V

  • 0°C ~ 70°C

  • 表面貼裝

  • 64-LQFP

  • 64-TQFP（10x10）

  • 托盤

  • 72285L20TF

IDT72285L20TF相關(guān)型號PDF文件下載

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