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IDT72251 Datasheet

  • IDT72251

  • CMOS SyncFIFO?

  • IDT

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CMOS SyncFIFO鈩?/div>
8192 X 9
Integrated Device Technology, Inc.
ADVANCED
INFORMATION
IDT72251
FEATURES:
鈥?/div>
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8192 x 9-bit organization
Pin/function compatible with IDT72421/722x1 family
15 ns read/write cycle time
Read and write clocks can be independent
Dual-Ported zero fall-through time architecture
Empty and Full flags signal FIFO status
Programmable Almost-Empty and Almost-Full flags can
be set to any depth
Programmable Almost-Empty and Almost-Full flags
default to Empty+7, and Full-7, respectively
Output enable puts output data bus in high-impedance
state
Advanced submicron CMOS technology
Available in 32-pin plastic leaded chip carrier (PLCC)
Industrial temperature range (-40
o
C to +85
o
C) is avail-
able, tested to military electrical specifications
DESCRIPTION:
The IDT72251 SyncFIFO鈩?is a very high-speed, low-
power First-In, First-Out (FIFO) memory with clocked read
and write controls. The IDT72251 has a 8192 x 9-bit memory
array. This FIFO is applicable for a wide variety of data
buffering needs such as graphics, local area networks and
interprocessor communication.
This FIFO has a 9-bit input and output port. The input port
is controlled by a free-running clock (WCLK), and two write
enable pins (
WEN1
, WEN2). Data is written into the
Synchronous FIFO on every rising clock edge when the write
enable pins are asserted. The output port is controlled by
another clock pin (RCLK) and two read enable pins (
REN1
,
REN2
). The read clock can be tied to the write clock for single
clock operation or the two clocks can run asynchronous of one
another for dual-clock operation. An output enable pin (
OE
) is
provided on the read port for three-state control of the output.
The Synchronous FIFO has two fixed flags, Empty (
EF
) and
Full (
FF
). Two programmable flags, Almost-Empty (
PAE
) and
Almost-Full (
PAF
), are provided for improved system control.
The programmable flags default to Empty+7 and Full-7 for
PAE
and
PAF
, respectively. The programmable flag offset
loading is controlled by a simple state machine and is initiated
by asserting the load pin (
LD
).
The IDT72251 is fabricated using IDT鈥檚 high-speed
submicron CMOS technology.
FUNCTIONAL BLOCK DIAGRAM
WCLK
WEN2
INPUT REGISTER
OFFSET REGISTER
D
0
- D
8
WRITE CONTROL
LOGIC
FLAG
LOGIC
WRITE POINTER
RAM ARRAY
8192 x 9
READ POINTER
READ CONTROL
LOGIC
OUTPUT REGISTER
RESET LOGIC
RCLK
Q
0
- Q
8
SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
3545 drw 01
COMMERCIAL TEMPERATURE RANGES
漏1996
Integrated Device Technology, Inc
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
DECEMBER 1996
DSC-3545/-
5.14
1

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