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IDT7200L25TPI Datasheet

  • IDT7200L25TPI

  • x9 Asynchronous FIFO

  • 14頁

  • ETC

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CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9, 1,024 x 9
IDT7200L
IDT7201LA
IDT7202LA
FEATURES:
鈥?/div>
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First-In/First-Out dual-port memory
256 x 9 organization (IDT7200)
512 x 9 organization (IDT7201)
1,024 x 9 organization (IDT7202)
Low power consumption
鈥?Active: 440mW (max.)
鈥擯ower-down: 28mW (max.)
Ultra high speed鈥?2ns access time
Asynchronous and simultaneous read and write
Fully expandable by both word depth and/or bit width
Pin and functionally compatible with 720X family
Status Flags: Empty, Half-Full, Full
Auto-retransmit capability
High-performance CEMOS鈩?technology
Military product compliant to MIL-STD-883, Class B
Standard Military Drawing #5962-87531, 5962-89666, 5962-89863
and 5962-89536 are listed on this function
Dual versions available in the TSSOP package. For more informa-
tion, see IDT7280/7281/7282 data sheet
IDT7280 = 2 x IDT7200
IDT7281 = 2 x IDT7201
IDT7282 = 2 x IDT7202
Industrial temperature range (鈥?0
o
C to +85
o
C) is available
(plastic packages only)
DESCRIPTION:
The IDT7200/7201/7202 are dual-port memories that load and empty
data on a first-in/first-out basis. The devices use Full and Empty flags to prevent
data overflow and underflow and expansion logic to allow for unlimited
expansion capability in both word size and depth.
The reads and writes are internally sequential through the use of ring
pointers, with no address information required to load and unload data. Data
is toggled in and out of the devices through the use of the Write (W) and Read
(R) pins.
The devices utilize a 9-bit wide data array to allow for control and parity bits
at the user鈥檚 option. This feature is especially useful in data communications
applications where it is necessary to use a parity bit for transmission/reception
error checking. It also features a Retransmit (RT) capability that allows for reset
of the read pointer to its initial position when
RT
is pulsed LOW to allow for
retransmission from the beginning of data. A Half-Full Flag is available in the
single device mode and width expansion modes.
These FIFOs are fabricated using IDT鈥檚 high-speed CMOS technology.
They are designed for those applications requiring asynchronous and
simultaneous read/writes in multiprocessing and rate buffer applications.
Military grade product is manufactured in compliance with the latest revision of
MIL-STD-883, Class B.
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FUNCTIONAL BLOCK DIAGRAM
DATA INPUTS
(D
0
-D
8
)
W
WRITE
CONTROL
WRITE
POINTER
RAM
ARRAY
256 x 9
512 x 9
1,024 x 9
READ
POINTER
R
READ
CONTROL
THREE-
STATE
BUFFERS
DATA OUTPUTS
(Q
0
-Q
8
)
RS
RESET
LOGIC
FL/RT
FLAG
LOGIC
EXPANSION
LOGIC
EF
FF
XI
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
XO/HF
2679 drw 01
COMMERCIAL, INDUSTRIAL AND MILITARY TEMPERATURE RANGES
1
2001
Integrated Device Technology, Inc.
MAY 2001
DSC-2679/8

IDT7200L25TPI 產(chǎn)品屬性

  • 14

  • 集成電路 (IC)

  • 邏輯 - FIFO

  • 7200

  • 異步

  • 2.3K(256 x 9)

  • 28.5MHz

  • 25ns

  • 4.5 V ~ 5.5 V

  • -40°C ~ 85°C

  • 通孔

  • 28-DIP(0.300",7.62mm)

  • 28-PDIP

  • 管件

  • 7200L25TPI

IDT7200L25TPI相關(guān)型號PDF文件下載

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    廠商
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