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IDT71V802S166PFI Datasheet

  • IDT71V802S166PFI

  • 256K X 36, 512K X 18 3.3V Synchronous SRAMs 2.5V I/O, Burst ...

  • 22頁

  • IDT

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256K X 36, 512K X 18
3.3V Synchronous SRAMs
2.5V I/O, Burst Counter
Pipelined Outputs, Single Cycle Deselect
x
x
IDT71V67602
IDT71V67802
Features
256K x 36, 512K x 18 memory configurations
Supports high system speed:
鈥?166MHz 3.5ns clock access time
鈥?150MHz 3.8ns clock access time
鈥?133MHz 4.2ns clock access time
LBO
input selects interleaved or linear burst mode
Self-timed write cycle with global write control (GW byte
GW),
GW
BWE
and byte writes (BW
BW
write enable (BWE
BWE),
BWx)
3.3V core power supply
Power down controlled by ZZ input
2.5V I/O supply (V
DDQ
)
Packaged in a JEDEC Standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array.
Description
The IDT71V67602/7802 are high-speed SRAMs organized as
256K x 36/512K x 18. The IDT71V676/78 SRAMs contain write, data,
address and control registers. Internal logic allows the SRAM to generate
a self-timed write based upon a decision which can be left until the end of
the write cycle.
The burst mode feature offers the highest level of performance to the
system designer, as the IDT71V67602/7802 can provide four cycles of
data for a single address presented to the SRAM. An internal burst address
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will be pipelined for one
cycle before it is available on the next rising clock edge. If burst mode
operation is selected (ADV=LOW), the subsequent three cycles of output
data will be available to the user on the next three rising clock edges. The
order of these three addresses are defined by the internal burst counter
and the
LBO
input pin.
The IDT71V67602/7802 SRAMs utilize IDT鈥檚 latest high-performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and 165 fine pitch ball grid array (fBGA).
x
x
x
x
x
x
Pin Description Summary
A
0
-A
18
Address Inputs
Chip Enable
Chip Selects
Output Enable
Global Write Enable
Byte Write Enable
Individual Byte Write Selects
Clock
Burst Address Advance
Address Status (Cache Controller)
Address Status (Processor)
Linear / Interleaved Burst Order
Sleep Mode
Data Input / Output
Core Power, I/O Power
Ground
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Supply
Supply
Synchronous
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Synchronous
Synchronous
DC
Asynchronous
Synchronous
N/A
N/A
5311 tbl 01
CE
CS
0
,
CS
1
OE
GW
BWE
BW
1
,
BW
2
,
BW
3
,
BW
4
(1)
CLK
ADV
ADSC
ADSP
LBO
ZZ
I/O
0
-I/O
31
, I/O
P1
-I/O
P4
V
DD
, V
DDQ
V
SS
NOTE:
1.
BW
3
and
BW
4
are not applicable for the IDT71V67802.
DECEMBER 2003
1
漏2002 Integrated Device Technology, Inc.
DSC-5311/07

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