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IDT71V432S6PF Datasheet

  • IDT71V432S6PF

  • 32K x 32 CacheRAM 3.3V Synchronous SRAM Burst Counter Single...

  • 18頁(yè)

  • IDT

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32K x 32 CacheRAM鈩?/div>
3.3V Synchronous SRAM
Burst Counter
Single Cycle Deselect
Features
x
x
IDT71V432
x
x
x
x
x
x
32K x 32 memory configuration
Supports high-performance system speed:
Commercial and Industrial:
鈥?5ns Clock-to-Data Access (100MHz)
鈥?6ns Clock-to-Data Access (83MHz)
鈥?7ns Clock-to-Data Access (66MHz)
Single-cycle deselect functionality (Compatible with
Micron Part # MT58LC32K32D7LG-XX)
LBO
input selects interleaved or linear burst mode
Self-timed write cycle with global write control (GW), byte
write enable (BWE), and byte writes (BWx)
Power down controlled by ZZ input
Operates with a single 3.3V power supply (+10/-5%)
Packaged in a JEDEC Standard 100-pin rectangular plastic
thin quad flatpack (TQFP).
Description
The IDT71V432 is a 3.3V high-speed 1,048,576-bit CacheRAM
organized as 32K x 32 with full support of the Pentium鈩?and PowerPC鈩?/div>
processor interfaces. The pipelined burst architecture provides cost-
effective 3-1-1-1 secondary cache performance for processors up to
100 MHz.
The IDT71V432 CacheRAM contains write, data, address, and
control registers. Internal logic allows the CacheRAM to generate a self-
timed write based upon a decision which can be left until the extreme end
of the write cycle.
The burst mode feature offers the highest level of performance to the
system designer, as the IDT71V432 can provide four cycles of data for
a single address presented to the CacheRAM. An internal burst address
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will be pipelined for one
cycle before it is available on the next rising clock edge. If burst mode
operation is selected (ADV=LOW), the subsequent three cycles of output
data will be available to the user on the next three rising clock edges. The
order of these three addresses will be defined by the internal burst counter
and the
LBO
input pin.
The IDT71V432 CacheRAM utilizes IDT's high-performance, high-
volume 3.3V CMOS process, and is packaged in a JEDEC Standard
14mm x 20mm 100-pin thin plastic quad flatpack (TQFP) for optimum board
density in both desktop and notebook applications.
Pin Description Summary
A
0
鈥揂
14
CE
CS
0
,
CS
1
OE
GW
BWE
BW
1,
BW
2,
BW
3,
BW
4
CLK
ADV
ADSC
ADSP
LBO
ZZ
I/O
0
鈥揑/O
31
V
DD
V
SS
Address Inputs
Chip Enable
Chips Selects
Output Enable
Global Write Enable
Byte Write Enable
Individual Byte Write Selects
Clock
Burst Address Advance
Address Status (Cache Controller)
Address Status (Processor)
Linear / Interleaved Burst Order
Sleep Mode
Data Input/Output
3.3V Power
Ground
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Power
Ground
Synchronous
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Synchronous
Synchronous
DC
Asynchronous
Synchronous
DC
DC
3104 tbl 01
CacheRAM is a trademark of Integrated Device Technology.
Pentium processor is a trademark of Intel Corp.
PowerPC is a trademark of International Business Machines, Inc.
AUGUST 2001
1
DSC-3104/05
漏2000 Integrated Device Technology, Inc.

IDT71V432S6PF 產(chǎn)品屬性

  • IDT71V432

  • 72

  • 集成電路 (IC)

  • 存儲(chǔ)器

  • -

  • RAM

  • SRAM - 同步

  • 1M（32K x 32）

  • 6ns

  • 并聯(lián)

  • 3.135 V ~ 3.63 V

  • 0°C ~ 70°C

  • 100-LQFP

  • 100-TQFP（14x14）

  • 托盤

  • 71V432S6PF

IDT71V432S6PF相關(guān)型號(hào)PDF文件下載

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