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IDT71V321S55TFI Datasheet

  • IDT71V321S55TFI

  • HIGH-SPEED 3.3V 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPT

  • 130.73KB

  • 14頁

  • IDT

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HIGH SPEED 3.3V
2K X 8 DUAL-PORT
STATIC RAM WITH INTERRUPTS
.eatures
x
IDT71V321S/L
IDT71V421S/L
x
x
High-speed access
鈥?Commercial: 25/35/55ns (max.)
鈥?Industrial: 25ns (max.)
Low-power operation
鈥?IDT71V321/IDT71V421S
鈥?/div>
Active: 325mW (typ.)
鈥?/div>
Standby: 5mW (typ.)
鈥?IDT71V321/V421L
鈥?/div>
Active: 325mW (typ.)
鈥?/div>
Standby: 1mW (typ.)
Two
INT
flags for port-to-port communications
x
x
x
x
x
x
x
x
MASTER IDT71V321 easily expands data bus width to 16-
or-more-bits using SLAVE IDT71V421
On-chip port arbitration logic (IDT71V321 only)
BUSY
output flag on IDT71V321;
BUSY
input on IDT71V421
Fully asynchronous operation from either port
Battery backup operation鈥?V data retention (L only)
TTL-compatible, single 3.3V power supply
Available in 52-pin PLCC, 64-pin TQFP and STQFP
packages
Industrial temperature range (鈥?0擄C to +85擄C) is available
for selected speeds
.unctional Block Diagram
OE
L
CE
L
R/W
L
OE
R
CE
R
R/W
R
I/O
0L
- I/O
7L
I/O
Control
BUSY
L
(1,2)
I/O
0R
-I/O
7R
I/O
Control
BUSY
R
A
10R
A
0R
(1,2)
A
10L
A
0L
Address
Decoder
11
MEMORY
ARRAY
11
Address
Decoder
CE
L
OE
L
R/W
L
ARBITRATION
and
INTERRUPT
LOGIC
CE
R
OE
R
R/W
R
INT
L
(2)
INT
R
3026 drw 01
(2)
NOTES:
1. IDT71V321 (MASTER):
BUSY
is an output. IDT71V421 (SLAVE):
BUSY
is input.
2.
BUSY
and
INT
are totem-pole outputs.
AUGUST 2001
1
漏2001 Integrated Device Technology, Inc.
DSC-3026/8

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