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IDT71V256SB12Y Datasheet

  • IDT71V256SB12Y

  • 3.3V CMOS FAST SRAM WITH 2.5V COMPATIBLE INPUTS 256K (32K x ...

  • 70.26KB

  • 6頁

  • IDT

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3.3V CMOS FAST SRAM
WITH 2.5V COMPATIBLE INPUTS
256K (32K x 8-BIT)
Integrated Device Technology, Inc.
IDT71V256SB
FEATURES
鈥?Ideal for high-performance processor secondary cache
鈥?Fast access times:
鈥?12/15/20ns
鈥?Inputs are 2.5V and LVTTL compatible: V
IH
= 1.8V
鈥?Outputs are LVTTL compatible
鈥?Low standby current (maximum):
鈥?2mA full standby
鈥?Small packages for space-efficient layouts:
鈥?28-pin 300 mil SOJ
鈥?28-pin TSOP Type I
鈥?Produced with advanced high-performance CMOS
technology
鈥?Single 3.3V(鹵0.3V) power supply
DESCRIPTION
The IDT71V256SB is a 262,144-bit high-speed static RAM
organized as 32K x 8. The improved V
IH
(1.8V) makes the
inputs compatible with 2.5V logic levels. The IDT71V256SB
is otherwise identical to the IDT71V256SA.
The IDT71V256SB has outstanding low power character-
istics while at the same time maintaining very high perfor-
mance. Address access times of as fast as12 ns are ideal for
tag SRAM in secondary cache designs.
When power management logic puts the IDT71V256SB in
standby mode, its very low power characteristics contribute to
extended battery life. By taking
CS
HIGH, the SRAM will
automatically go to a low power standby mode and will remain
in standby as long as
CS
remains HIGH. Furthermore, under
full standby mode (
CS
at CMOS level, f=0), power consump-
tion is guaranteed to always be less than 6.6mW and typically
will be much smaller.
The IDT71V256SB is packaged in 28-pin 300 mil SOJ and
28-pin300 mil TSOP Type I packaging.
FUNCTIONAL BLOCK DIAGRAM
A
0
ADDRESS
DECODER
A
14
262,144 BIT
MEMORY ARRAY
V
CC
GND
I/O
0
INPUT
DATA
CIRCUIT
I/O
7
I/O CONTROL
CS
OE
WE
CONTROL
CIRCUIT
3770 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGES
漏1997
Integrated Device Technology, Inc.
JANUARY 1997
7.??
3770/1
1

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