3.3V CMOS Static RAM
1 Meg (128K x 8-Bit)
Center Power &
Ground Pinout
x
x
IDT71V124SA
Features
128K x 8 advanced high-speed CMOS static RAM
JEDEC revolutionary pinout (center power/GND) for
reduced noise
Equal access and cycle times
鈥?Commercial: 10/12/15/20ns
鈥?Industrial: 10/12/15/20ns
One Chip Select plus one Output Enable pin
Inputs and outputs are LVTTL-compatible
Single 3.3V supply
Low power consumption via chip deselect
Available in a 32-pin 300- and 400-mil Plastic SOJ, and
32-pin Type II TSOP packages.
Description
The IDT71V124 is a 1,048,576-bit high-speed static RAM organized
as 128K x 8. It is fabricated using IDT鈥檚 high-performance, high-reliability
CMOS technology. This state-of-the-art technology, combined with inno-
vative circuit design techniques, provides a cost-effective solution for high-
speed memory needs. The JEDEC center power/GND pinout reduces
noise generation and improves system performance.
The IDT71V124 has an output enable pin which operates as fast as
5ns, with address access times as fast as 9ns available. All bidirec-
tional inputs and outputs of the IDT71V124 are LVTTL-compatible and
operation is from a single 3.3V supply. Fully static asynchronous
circuitry is used; no clocks or refreshes are required for operation.
x
x
x
x
x
x
Functional Block Diagram
A
0
鈥?/div>
鈥?/div>
鈥?/div>
A
16
ADDRESS
DECODER
鈥?/div>
鈥?/div>
鈥?/div>
1,048,576-BIT
MEMORY ARRAY
I/O
0
- I/O
7
8
8
I/O CONTROL
.
8
WE
OE
CS
CONTROL
LOGIC
3873 drw 01
NOVEMBER 2003
1
漏2003- Integrated Device Technology, Inc.
DSC-3873/07
IDT71V124SA10TYI相關(guān)型號PDF文件下載
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