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IDT71P72804S250BQ Datasheet

  • IDT71P72804S250BQ

  • 18Mb Pipelined QDRII SRAM Burst of 2

  • 22頁

  • IDT

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18Mb Pipelined
QDR鈩I SRAM
Burst of 2
Features
x
x
x
x
x
x
Description
Advance
Information
IDT71P72204
IDT71P72104
IDT71P72804
IDT71P72604
x
x
x
x
x
x
18Mb Density (2Mx8, 2Mx9, 1Mx18, 512kx36)
Separate, Independent Read and Write Data Ports
-
Supports concurrent transactions
Dual Echo Clock Output
2-Word Burst on all SRAM accesses
DDR (Double Data Rate) Multiplexed Address Bus
-
One Read and One Write request per clock cycle
DDR (Double Data Rate) Data Buses
-
Two word burst data per clock on each port
-
Four word transfers per clock cycle (2 word
bursts on 2 ports)
Depth expansion through Control Logic
HSTL (1.5V) inputs that can be scaled to receive signals
from 1.4V to 1.9V.
Scalable output drivers
-
Can drive HSTL, 1.8V TTL or any voltage level
from 1.4V to 1.9V.
-
Output Impedance adjustable from 35 ohms to 70
ohms
1.8V Core Voltage (V
DD
)
165-ball, 1.0mm pitch, 13mm x 15mm fBGA Package
JTAG Interface
The IDT QDRII
TM
Burst of two SRAMs are high-speed synchronous
memories with independent, double-data-rate (DDR), read and write
data ports. This scheme allows simultaneous read and write access for
the maximum device throughput, with two data items passed with each
read or write. Four data word transfers occur per clock cycle, providing
quad-data-rate (QDR) performance. Comparing this with standard SRAM
common I/O (CIO), single data rate (SDR) devices, a four to one in-
crease in data access is achieved at equivalent clock speeds. Consider-
ing that QDRII allows clock speeds in excess of standard SRAM de-
vices, the throughput can be increased well beyond four to one in most
applications.
Using independent ports for read and write data access, simplifies
system design by eliminating the need for bi-directional buses. All buses
associated with the QDRII are unidirectional and can be optimized for
signal integrity at very high bus speeds. The QDRII has scalable output
impedance on its data output bus and echo clocks, allowing the user to
tune the bus for low noise and high performance.
The QDRII has a single DDR address bus with multiplexed read and
write addresses. All read addresses are received on the first half of the
clock cycle and all write addresses are received on the second half of the
clock cycle. The read and write enables are received on the first half of
the clock cycle. The byte and nibble write signals are received on both
halves of the clock cycle simultaneously with the data they are controlling
on the data input bus.
The QDRII has echo clocks, which provide the user with a clock
Functional Block Diagram
(Note1)
D
(Note1)
DATA
REG
DATA
REG
(Note1)
WRITE DRIVER
SENSE AMPS
R
W
BW
x
(Note3)
CTRL
LOGIC
18M
MEMORY
ARRAY
(Note4)
OUTPUT REG
SA
(Note4)
OUTPUT SELECT
(Note2)
ADD
REG
(Note2)
WRITE/READ DECODE
(Note1)
Q
K
K
C
CLK
GEN
SELECT OUTPUT CONTROL
CQ
CQ
C
Notes
6109 drw 16
1) Represents 8 data signal lines for x8, 9 signal lines for x9, 18 signal lines for x18, and 36 signal lines for x36
2) Represents 20 address signal lines for x8 and x9, 19 address signal lines for x18, and 18 address signal lines for x36.
3) Represents 1 signal line for x9, 2 signal lines for x18, and four signal lines for x36. On x8 parts, the
BW
is a 鈥渘ibble write鈥?and there are 2
signal lines.
4) Represents 16 data signal lines for x8, 18 signal lines for x9, 36 signal lines for x18, and 72 signal lines for x36.
MAY 2004
1
漏2003 Integrated Device Technology, Inc.
鈥淨(jìng)DR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc. 鈥?/div>
DSC-6109/0C

IDT71P72804S250BQ 產(chǎn)品屬性

  • 136

  • 集成電路 (IC)

  • 存儲器

  • -

  • RAM

  • SRAM - 同步，QDR II

  • 18M（1M x 18）

  • 250MHz

  • 并聯(lián)

  • 1.7 V ~ 1.9 V

  • 0°C ~ 70°C

  • 165-TBGA

  • 165-CABGA（13x15）

  • 托盤

  • 71P72804S250BQ

IDT71P72804S250BQ相關(guān)型號PDF文件下載

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