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IDT7134SA25CI Datasheet

  • IDT7134SA25CI

  • HIGH-SPEED 4K x 8 DUAL-PORT STATIC SRAM

  • 11頁

  • IDT

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HIGH-SPEED
4K x 8 DUAL-PORT
STATIC SRAM
Features
High-speed access
聳 Military: 25/35/45/55/70ns (max.)
聳 Industrial: 55ns (max.)
聳 Commercial: 20/25/35/45/55/70ns (max.)
Low-power operation
聳 IDT7134SA
Active: 700mW (typ.)
Standby: 5mW (typ.)
聳 IDT7134LA
Active: 700mW (typ.)
Standby: 1mW (typ.)
Fully asynchronous operation from either port
Battery backup operation聴2V data retention
TTL-compatible; single 5V (鹵10%) power supply
Available in 48-pin DIP, LCC, Flatpack and 52-pin PLCC
Military product compliant to MIL-PRF-38535 QML
Industrial temperature range (聳40擄C to +85擄C) is available for
selected speeds
IDT7134SA/LA
Description
x
x
x
x
x
x
x
x
The IDT7134 is a high-speed 4K x 8 Dual-Port Static RAM
designed to be used in systems where on-chip hardware port arbitration
is not needed. This part lends itself to those systems which cannot
tolerate wait states or are designed to be able to externally arbitrate or
withstand contention when both sides simultaneously access the
same Dual-Port RAM location.
The IDT7134 provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access
for reads or writes to any location in memory. It is the user聮s responsibility
to ensure data integrity when simultaneously accessing the same
memory location from both ports. An automatic power down feature,
controlled by
CE,
permits the on-chip circuitry of each port to enter a
very low standby power mode.
Fabricated using IDT聮s CMOS high-performance technology, these
Dual-Port typically operate on only 700mW of power. Low-power (LA)
versions offer battery backup data retention capability, with each port
typically consuming 200碌W from a 2V battery.
The IDT7134 is packaged on either a sidebraze or plastic 48-pin
DIP, 48-pin LCC, 52-pin PLCC and 48-pin Flatpack. Military grade
product is manufactured in compliance with the latest revision of MIL-
PRF-38535 QML, making it ideally suited to military temperature
applications demanding the highest level of performance and reliability.
Functional Block Diagram
R/W
L
CE
L
R/W
R
CE
R
OE
L
I/O
0L
- I/O
7L
COLUMN
I/O
COLUMN
I/O
OE
R
I/O
0R
- I/O
7R
A
0L
- A
11L
LEFT SIDE
ADDRESS
DECODE
LOGIC
MEMORY
ARRAY
RIGHT SIDE
ADDRESS
DECODE
LOGIC
A
0R
- A
11R
2720 drw 01
JUNE 1999
1
DSC-2720/9

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