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IDT7130LA20PFGB Datasheet

  • IDT7130LA20PFGB

  • HIGH SPEED 1K X 8 DUAL-PORT STATIC SRAM

  • 155.62KB

  • 19頁

  • IDT

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HIGH SPEED
1K X 8 DUAL-PORT
STATIC SRAM
Features
High-speed access
鈥?Commercial: 20/25/35/55/100ns (max.)
鈥?Industrial: 25/55/100ns (max.)
鈥?Military: 25/35/55/100ns (max.)
Low-power operation
鈥?IDT7130/IDT7140SA
鈥?/div>
Active: 550mW (typ.)
鈥?/div>
Standby: 5mW (typ.)
鈥?IDT7130/IDT7140LA
鈥?/div>
Active: 550mW (typ.)
鈥?/div>
Standby: 1mW (typ.)
MASTER IDT7130 easily expands data bus width to 16-or-
more-bits using SLAVE IDT7140
IDT7130SA/LA
IDT7140SA/LA
鈼?/div>
鈼?/div>
鈼?/div>
鈼?/div>
鈼?/div>
鈼?/div>
鈼?/div>
鈼?/div>
鈼?/div>
鈼?/div>
鈼?/div>
鈼?/div>
鈼?/div>
On-chip port arbitration logic (IDT7130 Only)
BUSY
output flag on IDT7130;
BUSY
input on IDT7140
INT
flag for port-to-port communication
Fully asynchronous operation from either port
Battery backup operation鈥?V data retention (LA only)
TTL-compatible, single 5V 鹵10% power supply
Military product compliant to MIL-PRF-38535 QML
Industrial temperature range (鈥?0擄C to +85擄C) is available
for selected speeds
Available in 48-pin DIP, LCC and Ceramic Flatpack, 52-pin
PLCC, and 64-pin STQFP and TQFP
Green parts available, see ordering information
Functional Block Diagram
OE
L
CE
L
R/W
L
OE
R
CE
R
R/W
R
I/O
0L
- I/O
7L
I/O
Control
BUSY
L
(1,2)
I/O
0R
-I/O
7R
I/O
Control
BUSY
R
Address
Decoder
10
,
(1,2)
A
9L
A
0L
MEMORY
ARRAY
10
Address
Decoder
A
9R
A
0R
CE
L
OE
L
R/W
L
ARBITRATION
and
INTERRUPT
LOGIC
CE
R
OE
R
R/W
R
INT
L
(2)
INT
R
2689 drw 01
(2)
NOTES:
1. IDT7130 (MASTER):
BUSY
is open drain output and requires pullup resistor.
IDT7140 (SLAVE):
BUSY
is input.
2. Open drain output: requires pullup resistor.
APRIL 2006
1
DSC-2689/13
漏2006 Integrated Device Technology, Inc.

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