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IDT71215S9PF Datasheet

  • IDT71215S9PF

  • BiCMOS StaticRAM 240K (16K x 15-BIT) CACHE-TAG RAM For the P...

  • 14頁

  • IDT

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Integrated Device Technology, Inc.
BiCMOS StaticRAM
240K (16K x 15-BIT)
CACHE-TAG RAM
For the Pentium
鈩?/div>
Processor
IDT71215
FEATURES:
鈥?16K x 15 Configuration
鈥?12 TAG Bits
鈥?3 Separate I/O Status Bits (Valid, Dirty, Write Through)
鈥?Match output uses Valid bit to qualify MATCH output
鈥?High-Speed Address-to-Match comparison times
鈥?8/9/10/12ns over commercial temperature range
鈥?/div>
BRDY
circuitry included inside the Cache-Tag for highest
speed operation
鈥?Asynchronous Read/Match operation with Synchronous
Write and Reset operation
鈥?Separate
WE
for the TAG bits and the Status bits
鈥?Separate
OE
for the TAG bits, the Status bits, and
BRDY
鈥?Synchronous
RESET
pin for invalidation of all Tag entries
鈥?Dual Chip selects for easy depth expansion with no
performance degredation
鈥?I/O pins both 5V TTL and 3.3V LVTTL compatible with
V
CCQ
pins
鈥?/div>
PWRDN
pin to place device in low-power mode
鈥?Packaged in a 80-pin Thin Plastic Quad Flat Pack
(TQFP)
DESCRIPTION:
The IDT71215 is a 245,760-bit Cache Tag StaticRAM,
organized 16K x 15 and designed to support the Pentium and
other Intel processors at bus speeds up to 66MHz. There are
twelve common I/O TAG bits, with the remaining three bits
used as status bits. A 12-bit comparator is on-chip to allow fast
comparison of the twelve stored TAG bits and the current Tag
input data. An active HIGH MATCH output is generated when
these two groups of data are the same for a given address.
This high-speed MATCH signal, with t
ADM
as fast as 8ns,
provides the fastest possible enabling of secondary cache
accesses.
The three separate I/O status bits (VLD, DTY, and WT) can
be configured for either dedicated or generic functionality,
depending on the SFUNC input pin. With SFUNC LOW, the
status bits are defined and used internally by the device,
allowing easier determination of the validity and use of the
given Tag data. SFUNC HIGH releases the defined internal
status bit usage and control, allowing the user to configure the
status bit information to fit his system needs. A synchronous
RESET
pin, when held LOW at a rising clock edge, will reset
all status bits in the array for easy invalidation of all Tag
addresses.
The IDT71215 also provides the option for Burst Ready
(
BRDY
) generation within the cache tag itself, based upon
MATCH, VLD bit, WT bit, and external inputs provided by the
user. This can significantly simplify cache controller logic and
minimize cache decision time. Match and Read operations
are both asynchronous in order to provide the fastest access
times possible, while Write operations are synchronous for
ease of system timing.
The IDT71215 uses a 5V power supply on Vcc with sepa-
rate V
CCQ
pins provided for the outputs to offer compliance
with both 5.0V TTL and 3.3V LVTTL Logic levels. The
PWRDN
pin offers a low-power standby mode to reduce power con-
sumption by 90%, providing significant system power sav-
ings.
The IDT71215 is fabricated using IDT's high-performance,
high-reliability BiCMOS technology and is offered in a space-
saving 80-pin Thin Plastic Quad Flat Pack (TQFP) package.
PIN DESCRIPTIONS
A
0
鈥?A
13
Address Inputs
Chip Selects
Write Enable - Tag Bits
Write Enable - Status Bits
Output Enable - Tag Bits
Output Enable - Status Bits
Status Bit Reset
Powerdown Mode Control Pin
Status Bit Function Control Pin
Write/Read Input from Processor
Valid Bit / S
1
Bit Input
Dirty Bit / S
2
Bit Input
Write Through Bit / S
3
Bit Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
CLK
BRDYH
System Clock
Input
Input
Input
Input
Output
I/O
Output
Output
Output
Output
Pwr
QPwr
Gnd
3075 tbl 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Pentium is a trademark of Intel Corporation
CS1
, CS2
WET
WES
OET
OES
RESET
PWRDN
SFUNC
W/
R
VLD
IN
/ S
1IN
DTY
IN
/ S
2IN
WT
IN
/ S
3IN
BRDYOE
BRDYIN
BRDY
TAG
0
鈥?TAG
11
VLD
OUT
/ S
1OUT
DTY
OUT
/ S
2OUT
WT
OUT
/ S
3OUT
MATCH
V
CC
V
CCQ
V
SS
BRDY
Force High
BRDY
Output Enable
Additional
BRDY
Input
Burst Ready
Tag Data Input/Outputs
Valid Bit / S
1
Bit Output
Dirty Bit / S
2
Bit Output
Write Through Bit / S
3
Bit Output
Match
+5V Power
Output Buffer Power
Ground
COMMERCIAL TEMPERATURE RANGE
漏1996
Integrated Device Technology, Inc.
AUGUST 1996
DSC-3075/3
14.3
1

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