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IDT71128S20Y Datasheet

  • IDT71128S20Y

  • CMOS Static RAM 1 Meg (256K x 4-Bit) Revolutionary Pinout

  • 8頁(yè)

  • IDT

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CMOS Static RAM
1 Meg (256K x 4-Bit)
Revolutionary Pinout
Features
x
x
IDT71128
Description
The IDT71128 is a 1,048,576-bit high-speed static RAM
organized as 256K x 4. It is fabricated using IDT鈥檚 high-perfor-
mance, high-reliability CMOS technology. This state-of-the-art
technology, combined with innovative circuit design techniques,
provides a cost-effective solution for high-speed memory needs.
The JEDEC centerpower/GND pinout reduces noise generation
and improves system performance.
The IDT71128 has an output enable pin which operates as fast
as 6ns, with address access times as fast as 12ns available. All
bidirectional inputs and outputs of the IDT71128 are TTL-compat-
ible and operation is from a single 5V supply. Fully static asyn-
chronous circuitry is used; no clocks or refreshes are required for
operation.
The IDT71128 is packaged in a 32-pin 400 mil Plastic SOJ.
x
x
x
x
x
256K x 4 advanced high-speed CMOS static RAM
JEDEC revolutionary pinout (center power/GND) for
reduced noise.
Equal access and cycle times
鈥?Commercial and Industrial: 12/15/20ns
One Chip Select plus one Output Enable pin
Bidirectional inputs and outputs directly
TTL-compatible
Low power consumption via chip deselect
Available in a 32-pin 400 mil Plastic SOJ.
Functional Block Diagram
A
0
ADDRESS
DECODER
1,048,576-BIT
MEMORY
ARRAY
.
A
17
4
4
I/O
0
- I/O
3
I/O CONTROL
CS
WE
OE
CONTROL
LOGIC
3483 drw 01
FEBRUARY 2001
1
漏2000 Integrated Device Technology, Inc.
DSC-3483/09

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