鈼?/div>
Full synchronous operation on both ports
鈥?3.5ns setup to clock and 0ns hold on all control, data, and
address inputs
鈥?Data input, address, and control registers
鈥?Fast 6.5ns clock to data out in the Pipelined output mode
鈥?Self-timed write allows fast cycle time
鈥?10ns cycle time, 100MHz operation in Pipelined output mode
Separate upper-byte and lower-byte controls for
multiplexed bus and bus matching compatibility
LVTTL- compatible, single 3.3V (鹵0.3V) power supply
Industrial temperature range (鈥?0擄C to +85擄C) is
available for 83 MHz
Available in a 100-pin Thin Quad Flatpack (TQFP) and 100-
pin Fine Pitch Ball Grid Array (fpBGA) packages.
Functional Block Diagram
R/
W
L
UB
L
CE
0L
R/
W
R
UB
R
CE
0R
CE
1L
LB
L
OE
L
1
0
0/1
1
0
0/1
CE
1R
LB
R
OE
R
FT
/PIPE
L
0/1
1b 0b
b a
1a 0a
0a 1a
a
b
0b 1b
0/1
FT
/PIPE
R
I/O
9L
-I/O
17L
I/O
0L
-I/O
8L
I/O
Control
I/O
9R
-I/O
17R
I/O
Control
I/O
0R
-I/O
8R
A
12L
(1)
A
0L
CLK
L
Counter/
Address
Reg.
MEMORY
ARRAY
Counter/
Address
Reg.
A
12R
(1)
A
0R
CLK
R
ADS
L
CNTEN
L
CNTRST
L
ADS
R
CNTEN
R
CNTRST
R
5638 drw 01
NOTE:
1. A
12
is a NC for IDT70V9349.
AUGUST 2003
1
漏2003 Integrated Device Technology, Inc.
DSC-5638/3