鈼?/div>
additional logic
Full synchronous operation on both ports
鈥?4ns setup to clock and 0ns hold on all control, data, and
address inputs
鈥?Data input, address, and control registers
鈥?Fast 6.5ns clock to data out in the Pipelined output mode
鈥?Self-timed write allows fast cycle time
鈥?10ns cycle time, 100MHz operation in Pipelined output mode
LVTTL- compatible, single 3.3V (鹵0.3V) power supply
Industrial temperature range (鈥?0擄C to +85擄C) is
available for selected speeds
Available in a 100-pin Thin Quad Flatpack (TQFP)
Functional Block Diagram
R/W
OE
L
CE
0L
CE
1L
R/W
R
OE
R
CE
0R
CE
1R
1
0
0/1
1
0
0/1
FT/PIPE
L
0/1
1
0
0
1
0/1
FT/PIPE
R
,
I/O
0L
- I/O
8L
I/O
Control
I/O
Control
I/O
0R
- I/O
8R
A
15L
(1)
A
0L
CLK
L
ADS
L
CNTEN
L
CNTRST
L
Counter/
Address
Reg.
MEMORY
ARRAY
Counter/
Address
Reg.
A
15R
(1)
A
0R
CLK
R
ADS
R
CNTEN
R
CNTRST
R
4860 drw 01
NOTE:
1. A
15
X
is a NC for IDT70V9179.
FEBRUARY 2004
1
漏2004 Integrated Device Technology, Inc.
DSC-4860/3