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IDT70V7319S200DDI Datasheet

  • IDT70V7319S200DDI

  • HIGH-SPEED 3.3V 256K x 18 SYNCHRONOUS BANK-SWITCHABLE DUAL-P...

  • 620.40KB

  • 22頁(yè)

  • IDT

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HIGH-SPEED 3.3V 256K x 18
SYNCHRONOUS
BANK-SWITCHABLE
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
Features:
鈼?/div>
IDT70V7319S
鈼?/div>
鈼?/div>
鈼?/div>
鈼?/div>
鈼?/div>
鈼?/div>
256K x 18 Synchronous Bank-Switchable Dual-ported
SRAM Architecture
鈥?/div>
64 independent 4K x 18 banks
鈥?4 megabits of memory on chip
Bank access controlled via bank address pins
High-speed data access
鈥?Commercial: 3.4ns (200MHz)/3.6ns (166MHz)/
4.2ns (133MHz) (max.)
鈥?Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)
Selectable Pipelined or Flow-Through output mode
Counter enable and repeat features
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
鈥?5ns cycle time, 200MHz operation (14Gbps bandwidth)
鈥?Fast 3.4ns clock to data out
鈥?1.5ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 200MHz
鈼?/div>
鈼?/div>
鈼?/div>
鈼?/div>
鈼?/div>
鈼?/div>
鈥?Data input, address, byte enable and control registers
鈥?Self-timed write allows fast cycle time
Separate byte controls for multiplexed bus and bus
matching compatibility
LVTTL- compatible, 3.3V (鹵150mV) power supply
for core
LVTTL compatible, selectable 3.3V (鹵150mV) or 2.5V
(鹵100mV) power supply for I/Os and control signals on
each port
Industrial temperature range (-40擄C to +85擄C) is
available at 166MHz and 133MHz
Available in a 144-pin Thin Quad Flatpack (TQFP),
208-pin fine pitch Ball Grid Array (fpBGA), and 256-pin Ball
Grid Array (BGA)
Supports JTAG features compliant with IEEE 1149.1
鈥?/div>
Due
to limited pin count, JTAG is not supported on the
144-pin TQFP package.
Functional Block Diagram
PL/FT
L
OPT
L
CLK
L
ADS
L
CNTEN
L
REPEAT
L
R/W
L
CE
0L
CE
1L
UB
L
LB
L
OE
L
PL/FT
R
OPT
R
CLK
R
ADS
R
CNTEN
R
REPEAT
R
R/W
R
CE
0R
CE
1R
UB
R
LB
R
OE
R
CONTROL
LOGIC
MUX
4Kx18
MEMORY
ARRAY
(BANK 0)
MUX
CONTROL
LOGIC
I/O
0L-17L
I/O
CONTROL
MUX
4Kx18
MEMORY
ARRAY
(BANK 1)
MUX
I/O
CONTROL
I/O
0R-17R
A
11L
A
0L
BA
5L
BA
4L
BA
3L
BA
2L
BA
1L
BA
0L
ADDRESS
DECODE
ADDRESS
DECODE
A
11R
A
0R
BA
5R
BA
4R
BA
3R
BA
2R
BA
1R
BA
0R
BANK
DECODE
MUX
4Kx18
MEMORY
ARRAY
(BANK 63)
BANK
DECODE
NOTE:
1. The Bank-Switchable dual-port uses a true SRAM
core instead of the traditional dual-port SRAM core.
As a result, it has unique operating characteristics.
Please refer to the functional description on page 19
for details.
MUX
,
TDI
TDO
JTAG
TMS
TCK
TRST
5629 drw 01
DECEMBER 2002
1
DSC 5629/6
漏2002 Integrated Device Technology, Inc.

IDT70V7319S200DDI相關(guān)型號(hào)PDF文件下載

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